STEVAL-ISQ002V1 STMicroelectronics, STEVAL-ISQ002V1 Datasheet - Page 118

• Manufacturer Part Number: STEVAL-ISQ002V1
• Description: BOARD EVAL BASED ON ST72264G1
• Manufacturer: STMicroelectronics

Specifications of STEVAL-ISQ002V1

• Main Purpose: Interface, PMBus
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST72F264
• Primary Attributes: The PMBus™ Interface Using the ST7 I2C Peripheral
• Secondary Attributes: Firmware in C Language
• Product: Power Management Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-6423

ST72260Gx, ST72262Gx, ST72264Gx
10-BIT A/D CONVERTER (ADC) (Cont’d)
11.7.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by soft-
ware reading the ADCDRH register or writing to
any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED A/D clock selection
This bit is set and cleared by software.
Table 22. A/D Clock Selection
1)
setting the ADON bit.
2)
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
Bit 4 = SLOW A/D Clock Selection
This bit is set and cleared by software. It works to-
gether with the SPEED bit. Refer to
118/172
EOC SPEED ADON SLOW
The SPEED and SLOW bits must be updated before
Use this setting only if f
7
f
f
CPU
ADC
(See Note 2)
Frequency
f
f
CPU
CPU
/2
/4
CPU
≤
4 MHz
0
SLOW
CH2
(See Note 1)
0
1
0
1
Table
CH1
SPEED
22.
1
1
0
0
CH0
0
Bit 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
DATA REGISTER (ADCDRH)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[9:2] MSB of Analog Converted Value
DATA REGISTER (ADCDRL)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0] LSB of Analog Converted Value
D9
7
7
0
D8
0
Channel Pin
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
D7
0
D6
0
D5
0
CH2
0
0
0
0
1
1
D4
0
CH1
0
0
1
1
0
0
D3
D1
CH0
D2
D0
0
1
0
1
0
1
0
0