STEVAL-ISQ002V1 STMicroelectronics, STEVAL-ISQ002V1 Datasheet - Page 25

• Manufacturer Part Number: STEVAL-ISQ002V1
• Description: BOARD EVAL BASED ON ST72264G1
• Manufacturer: STMicroelectronics

Specifications of STEVAL-ISQ002V1

• Main Purpose: Interface, PMBus
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST72F264
• Primary Attributes: The PMBus™ Interface Using the ST7 I2C Peripheral
• Secondary Attributes: Firmware in C Language
• Product: Power Management Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-6423

SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2 Auxiliary Voltage Detector (AVD)
The Voltage Detector function (AVD) is based on
an analog comparison between a V
erence value and the V
reference value for falling voltage is lower than the
V
avoid parasitic detection (hysteresis).
The output of the AVD comparator is directly read-
able by the application software through a real
time status bit (VDF) in the SICSR register. This bit
is read only.
Caution: The AVD functions only if the LVD is en-
abled through the option byte.
6.4.2.1 Monitoring the V
The AVD voltage threshold value is relative to the
selected LVD threshold configured by option byte
(see
If the AVD interrupt is enabled, an interrupt is gen-
erated when the voltage crosses the V
V
Figure 15. Using the AVD to Monitor V
IT+
IT-(AVD)
AVDF bit
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
LVD RESET
V
V
V
reference value for rising voltage in order to
Section 15.1 on page
V
IT+(AVD)
IT+(LVD)
IT-(LVD)
IT-(AVD)
threshold (AVDF bit toggles).
V
DD
0
DD
DD
162).
main supply. The V
Main Supply
1
IT-
INTERRUPT PROCESS
and V
IT+(AVD)
V
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
DD
hyst
IT+
RESET VALUE
ref-
IT-
or
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcon-
troller. See
The interrupt on the rising edge is used to inform
the application that the V
If the voltage rise time t
CPU cycles (depending on the reset delay select-
ed by option byte), no AVD interrupt will be gener-
ated when V
If t
– If the AVD interrupt is enabled before the
– If the AVD interrupt is enabled after the V
V
rupts will be received: the first when the AVDIE
bit is set, and the second when the threshold is
reached.
threshold is reached then only one AVD interrupt
will occur.
rv
IT+(AVD)
is greater than 256 or 4096 cycles then:
ST72260Gx, ST72262Gx, ST72264Gx
threshold is reached, then 2 AVD inter-
Figure
IT+(AVD)
t
1
15.
rv
VOLTAGE RISE TIME
is reached.
rv
DD
is less than 256 or 4096
warning state is over.
INTERRUPT PROCESS
0
IT+(AVD)
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