SOUNDBITE Freescale Semiconductor, SOUNDBITE Datasheet
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... DSP56371 Overview 2.1 Introduction This manual describes the DSP56371 24-bit digital signal processor (DSP), its memory, operating modes and peripheral modules. The DSP56371 is a member of © Freescale Semiconductor, Inc., 2004, 2005, 2006, 2007. All rights reserved. Rev. 4.1, 1/2007 Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 DSP56371 Overview ...
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... Memory Expansion Area X Data Y Data RAM RAM 36K × 24 48K × 24 ROM ROM 32K × 24 32K × 24 YAB XAB PAB DAB 24-Bit Core Power Mgmt. Data ALU JTAG 24 × → 56-bit MAC OnCE™ Two 56-bit Accumulators 56-bit Barrel Shifter Freescale Semiconductor 4 ...
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... Up to 32Kx24 Bit from Y Data RAM and 8Kx24 Bit from X Data RAM can be switched to Program RAM resulting 44Kx24 Bit of Program RAM. • Peripheral modules — Enhanced Serial Audio Interface (ESAI receivers and transmitters, master or Freescale Semiconductor DSP56371 User’s Manual, Memory Configuration DSP56371 Data Sheet, Rev. 4.1 DSP56371 Overview Section 2.4 DSP56300 Core section ...
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... DMA controller (with six channels) • Instruction patch controller • PLL-based clock oscillator • OnCE module • Memory protocols, multi master capability in I Section 2.4.7 On-Chip Memory DSP56371 Data Sheet, Rev. 4 mode, for more details about memory size. Freescale Semiconductor ...
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... The 48-bit product is right-justified and added to the 56-bit contents of either the accumulator. A 56-bit result can be stored as a 24-bit operand. The LSP can either be truncated or rounded into the MSP. Rounding is performed if specified. Freescale Semiconductor DSP56371 Data Sheet, Rev. 4.1 DSP56371 Overview Section 2 ...
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... PCU features include the following: • Position independent code support • Addressing modes optimized for DSP applications (including immediate offsets) • On-chip instruction cache controller • On-chip memory-expandable hardware stack • Nested hardware DO loops • Fast auto-return interrupts 6 DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor ...
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... Direct Memory Access (DMA) The DMA block has the following features: • Six DMA channels supporting internal and external accesses • One-, two- and three-dimensional transfers (including circular buffering) • End-of-block-transfer interrupts Freescale Semiconductor DSP56371 Data Sheet, Rev. 4.1 DSP56371 Overview Figure 1. 7 ...
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... There are on-chip ROMs for program and bootstrap memory (64K x 24-bit), X ROM (32K x 24-bit) and Y ROM (32K x 24-bit). More information on the internal memory is provided in the 2.4.8 Off-Chip Memory Expansion Memory cannot be expanded off-chip. There is no external memory bus. 8 NOTE DSP56371 User’s Manual, Memory DSP56371 Data Sheet, Rev. 4.1 Section 3, DSP56371 section. Freescale Semiconductor ...
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... Enhanced Serial Audio Interface (ESAI) The ESAI provides a full-duplex serial port for serial communication with a variety of serial devices including one or more industry-standard codecs, other DSPs, microprocessors and peripherals that Freescale Semiconductor 2 S, Sony, AC97, network and other programmable 2 C protocols, with multi-master capability, 10-word DSP56371 Data Sheet, Rev ...
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... V. A special notice for this feature is added to the signal descriptions of those inputs. 10 section. DSP56371 User’s Manual, Enhanced Serial Audio Interface (ESAI_1 bus. The SHI supports either the SPI or I section. DSP56371 User’s Manual, Digital Audio DSP56371 Data Sheet, Rev. 4.1 DSP56371 User’ bus protocol, as required, Freescale Semiconductor ...
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... Port C signals are the GPIO port signals which are multiplexed with the ESAI signals. 2. Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals. 3. Port D signals are the GPIO port signals which are multiplexed with the DAX signals. 4. Port F signals are the dedicated GPIO port signals. Freescale Semiconductor 1 Port C 2 ...
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... MISO/HDA SCK/SCL HREQ TIO0 TIMER TIO1 SCKT ESAI FST HCKT SCKR FSR HCKR SDO0 SDO1 SDO2/SDI3 SDO3/SDI2 SDO4/SDI1 SDO5/SDI0 SCKT_1 ESAI_1 FST_1 HCKT_1 SCKR_1 FSR_1 HCKR_1 SDO0_1 SDO1_1 SDO2_1/SDI3_1 SDO3_1/SDI2_1 SDO4_1/SDI1_1 SDO5_1/SDI0_1 PERIPHERAL I/O POWER IO_VDD (5) IO_GNDS (5) SCAN SCAN Freescale Semiconductor ...
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... PF7 CORE_GND PF2 PF3 PF4 PF5 IO_VDD PF1 PF0 IO_GND 3.3V Freescale Semiconductor Table 2. Power Inputs Description power rail. The user must provide adequate external DD power rail. The user must provide adequate DD power rail. The user must provide adequate DD ESAI DAX ...
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... PLL is enabled or disabled. After RESET de assertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized to internal system clock. Internal Pull up resistor. This input tolerant. DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor ...
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... During Reset MODA/IRQA Input Input Freescale Semiconductor Table 6. Interrupt and Mode Control Signal Description Mode Select A/External Interrupt Request A—MODA/IRQA is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing ...
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... MODA, MODB, MODC and MODD inputs. The RESET signal must be asserted during power up. A stable EXTAL signal must be supplied while RESET is being asserted. Internal Pull up resistor. This input tolerant. DSP56371 Data Sheet, Rev. 4 mode. Freescale Semiconductor ...
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... SDA Input or open-drain output Freescale Semiconductor Table 7. Serial Host Interface Signals Signal Description master and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer ...
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... HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for an external pull-up in this state. Internal Pull up resistor. This input tolerant. DSP56371 Data Sheet, Rev. 4 slave mode, the HA0 signal is used master 2 C Slave mode, the HA2 signal is used 2 C master mode. Freescale Semiconductor ...
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... Input, output, or disconnected HCKT Input or output PC5 Input, output, or disconnected Freescale Semiconductor State during Reset GPIO High Frequency Clock for Receiver—When programmed as an disconnected input, this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock. When ...
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... ESAI transmit clock control register (TCCR). Port C4—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input tolerant. DSP56371 Data Sheet, Rev. 4.1 Signal Description Freescale Semiconductor ...
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... SDO5 Output SDI0 Input PC6 Input, output, or disconnected Freescale Semiconductor State during Reset GPIO Receiver Serial Clock—SCKR provides the receiver serial bit disconnected clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0 serial flag 0 pin in the synchronous mode (SYN=1) ...
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... RX3 serial receive shift register. Port C9—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input tolerant. DSP56371 Data Sheet, Rev. 4.1 Signal Description Freescale Semiconductor ...
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... PC10 Input, output, or disconnected SDO0 Output PC11 Input, output, or disconnected Freescale Semiconductor State during Reset GPIO Serial Data Output 1—SDO1 is used to transmit data from the TX1 disconnected serial transmit shift register. Port C10—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected ...
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... DACs additional system clock. Port E5—When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input tolerant. DSP56371 Data Sheet, Rev. 4.1 Signal Description Freescale Semiconductor ...
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... Input, output, or disconnected FST_1 Input or output PE4 Input, output, or disconnected Freescale Semiconductor State during Reset GPIO Frame Sync for Receiver_1—This is the receiver frame sync disconnected input/output signal. In the asynchronous mode (SYN=0), the FSR_1 pin operates as the frame sync input or output used by all the enabled receivers ...
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... SDI0_1 is used to receive serial data into the RX0 serial receive shift register. Port E6—When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input tolerant. DSP56371 Data Sheet, Rev. 4.1 Signal Description Freescale Semiconductor ...
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... SDO2_1 Output SDI3_1 Input PE9 Input, output, or disconnected Freescale Semiconductor State during Reset GPIO Serial Data Output 4_1—When programmed as a transmitter, disconnected SDO4_1 is used to transmit data from the TX4 serial transmit shift register. Serial Data Input 1_1—When programmed as a receiver, SDI1_1 is used to receive serial data into the RX1 serial receive shift register ...
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... TX0 serial transmit shift register. Port E11—When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input tolerant. DSP56371 Data Sheet, Rev. 4.1 Signal Description Freescale Semiconductor ...
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... ADO Output PD1 Input, output, or disconnected Freescale Semiconductor State During Reset GPIO Audio Clock Input—This is the DAX clock input. When Disconnected programmed to use an external clock, this input supplies the DAX clock. The external clock frequency must be 256, 384, or 512 times the audio sampling frequency (256 × ...
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... Internal Pull down resistor. This input tolerant. GPIO Port F6—this signal is individually programmable as input, output, disconnected or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input tolerant. DSP56371 Data Sheet, Rev. 4.1 Signal Description Freescale Semiconductor ...
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... PF9 Input, output, or disconnected PF10 Input, output, or disconnected Freescale Semiconductor State During Reset GPIO Port F7— this signal is individually programmable as input, output, disconnected or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input tolerant. ...
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... GPIO output immediately at the beginning of operation or leave it defined as GPIO input but connected to Vdd through a pull-up resistor in order to ensure a stable logic level at this input. Internal Pull down resistor. This input tolerant. DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor ...
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... Therefore, a “maximum” value for a specification will never occur in the same device that has a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. Freescale Semiconductor Table 13. JTAG/OnCE Interface Signal Description Test Clock— ...
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... V IN and GND SCK I DAX Ijtag STG = 0°C to 100°C for 181 MHz 50PF J IO VDD External Schottky DSP56371 Data Sheet, Rev. 4 Value Unit − 0 1.6 V − 0 4.0 V − GND 0 ° –40 to +115 C − ° +125 C Diode Freescale Semiconductor ...
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... Input leakage current (All pins) Clock pin Input Capacitance (EXTAL) High impedance (off-state) input current (@ 3.46 V) Output high voltage Output low voltage Internal supply current at internal clock of 181MHz • In Normal mode Freescale Semiconductor Table 15. Thermal Characteristics Symbol or θ R θ θ R θJC JC Symbol Min V 1 ...
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... CORE_VDD DD_IO = 1. 3.46V 115°C. IO_VDD 0°C to 100°C for 181 MHz; CL=50pF J NOTE DSP56371 Data Sheet, Rev. 4.1 4 Typ Max Unit 48 150 mA 2 — 25°C. Maximum internal supply current is J maximum IL and V OL Freescale Semiconductor OH ...
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... Maximum frequency will vary depending on the ordered part number. 10 External Clock Operation The DSP56371 system clock is an externally supplied square wave voltage source connected to EXTAL (see Figure 4.). EXTAL ETH V IL Note: The midpoint is 0.5 (V Freescale Semiconductor Table 17. INTERNAL CLOCKS Symbol Min Typ 1 Fref 5 — FIN Fref*NR (1000/Etc × FM)/ FOUT 75 (PDF × ...
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... Min Max — 11 11.1 — — 5.5 C 11.1 — C 5.0 LOCK 10.0 — 10.0 — 11.1 — C 11.1 — C Freescale Semiconductor inf inf Unit ...
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... RESET duration” conditions (as specified above) have not been yet DD met, the device circuitry will uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. Freescale Semiconductor Reset, Stop, Mode Select, and Interrupt Timing Expression 10 xT ...
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... Figure 6. Recovery from Stop State Using IRQA Interrupt Service IRQA, IRQB, IRQC, IRQD, NMI IRQA, IRQB, IRQC, IRQD, NMI Figure 7. External Interrupt Timing (Negative Edge-Triggered Reset Value Figure 5. Reset Timing DSP56371 Data Sheet, Rev. 4 IRQA, IRQB, IH IRQD, NMI V IL Freescale Semiconductor ...
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... SCK last sampling edge to data input not valid 31 SS assertion to data out active 32 SS deassertion to data high impedance 33 SCK edge to data out valid (data out delay time) Freescale Semiconductor First Interrupt Instruction Execution 20 b) General Purpose I/O Figure 8. External Fast Interrupt Timing 1,3,4 ...
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... Figure 9. SPI Master Timing (CPHA = 0) DSP56371 Data Sheet, Rev. 4.1 Expressions Min Max 2 12.0 — C — — 15.0 3 — 52.2 — 46.6 — 12.7 — 3.0 63.0 — SPICC — 0 — — 0 — Freescale Semiconductor Unit ...
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... SS (Input) SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) 29 MISO (Input) MOSI (Output) 40 HREQ (Input) Freescale Semiconductor MSB Valid 33 MSB 42 43 DSP56371 Data Sheet, Rev. 4.1 Serial Host Interface SPI Protocol Timing LSB Valid 34 LSB 43 ...
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... Serial Host Interface SPI Protocol Timing SS (Input) SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) MISO (Input) MOSI (Output) 40 HREQ (Input MSB Valid 33 MSB Figure 10. SPI Master Timing (CPHA = 1) DSP56371 Data Sheet, Rev. 4 LSB Valid 34 LSB Freescale Semiconductor ...
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... SS (Input) SCK (CPOL = 0) (Input) SCK (CPOL = 1) (Input MISO (Output) 29 MOSI (Input) HREQ (Output) Freescale Semiconductor MSB 30 MSB Valid 36 Figure 11. SPI Slave Timing (CPHA = 0) DSP56371 Data Sheet, Rev. 4.1 Serial Host Interface SPI Protocol Timing LSB 29 30 LSB Valid 38 45 ...
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... Freescale Semiconductor Unit kHz µs µs µs µs µs µ ...
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... HRS is the pre-scaler rate select bit. When HRS is cleared, the fixed divide-by-eight pre-scaler is operational. When HRS is set, the pre-scaler is bypassed. — HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be selected. Freescale Semiconductor Serial Host Interface (SHI Protocol Timing (continued) ...
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... SSICCH 2 × × SSICCL 2 × × — — — — DSP56371 Data Sheet, Rev. 4.1 Eqn. 2 Eqn. 3 ACK Stop Min Max Condition Unit 22.3 — 22.3 — 12.0 — ns 12.0 — 12.0 — ns 12.0 — — 37 — 22 — 37 — 22 Freescale Semiconductor ...
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... SCKT edge to FST out (wl) high 83 SCKT edge to FST out (wl) low 84 SCKT edge to data out enable from high impedance 85 SCKT edge to transmitter #0 drive enable assertion 86 SCKT edge to data out valid 87 SCKT edge to data out high impedance Freescale Semiconductor Symbol Expression 6 — — 6 — ...
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... MHz DSP56371 Data Sheet, Rev. 4.1 Min Max Condition — 34 — 20 2.0 — 21.0 — 2.0 — 21.0 — 4.0 — 0.0 — — 27.0 — — 31.0 — — 32 — 18 13.4 — C — 18.0 — 18 Freescale Semiconductor 4 Unit ...
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... In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. Figure 14 is drawn assuming positive polarity bit clock (TCKP=0) and positive frame sync polarity (TFSP=0). Freescale Semiconductor 62 64 ...
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... HCKT SCKT (output) Note: Figure 16 is drawn assuming positive polarity high frequency clock (THCKP=0) and positive bit clock polarity (TCKP=0 First Bit Figure 15. ESAI Receiver Timing 96 97 Figure 16. ESAI HCKT Timing DSP56371 Data Sheet, Rev. 4 Last Bit 75 77 Freescale Semiconductor ...
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... In order to assure proper operation of the DAX, the ACI frequency should be less than 1/2 of theDSP56371 internal clock frequency. For example, if the DSP56371 is running at 181 MHz internally, the ACI frequency should be less than 90MHz. ACI 103 ADO Freescale Semiconductor 96 98 Figure 17. ESAI HCKR Timing Table 23. Digital Audio Transmitter Timing Expression ...
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... MHz 0°C to 100°C for 181 MHz Figure 20. GPIO Timing DSP56371 Data Sheet, Rev. 4.1 181 MHz Unit Min Max 13 — — Min Max Unit — — — — — 33 33 — — — — Freescale Semiconductor ...
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... TCK low to TDO high impedance Note: = 1.25 V ± 0. CORE_VDD All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. TCK (Input) 119 Freescale Semiconductor Table 26. JTAG Timing Characteristics × 6); maximum 22 MHz –40°C to 115°C for 150 MHz 117 118 ...
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... Input Data Valid 120 Output Data Valid 121 120 Output Data Valid Figure 22. Debugger Port Timing Diagram 122 Input Data Valid 124 Output Data Valid 125 124 Output Data Valid DSP56371 Data Sheet, Rev. 4.1 VIH 123 VIH 123 Freescale Semiconductor ...
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... SDO0_PC11 8 CORE_VDD 9 PF8 10 PF6 11 PF7 12 CORE_GND 13 PF2 GPIO 14 PF3 15 PF4 16 PF5 17 IO_VDD 18 PF1 19 PF0 20 GND Freescale Semiconductor . ESAI DAX Timer OnCE Figure 24. DSP56371 Pinout DSP56371 Data Sheet, Rev. 4.1 Package Information ESAI_1 60 FST_PE4 59 SDO5_SDI0_PE6 58 SDO4_SDI1_PE7 57 SDO3_SDI2_PE8 56 SDO2_SDI3_PE9 55 SDO1_PE10 54 SDO0_PE11 53 CORE_GND 52 CORE_VDD ...
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... SCK_SCL 56 SDO2_SDI3_PE9 37 SS_HA2 57 SDO3_SDI2_PE8 38 HREQ 58 SDO4_SDI1_PE7 39 PLLA_VDD 59 SDO5_SD10_PE6 40 PLLA_GND 60 FST_PE4 DSP56371 Data Sheet, Rev. 4.1 Pin Signal Name No. 61 FSR_PE1 62 SCKT_PE3 63 SCKR_PE0 64 IO_VDD 65 IO_GND 66 HCKT_PE5 67 HCKR_PE2 68 CORE_GND 69 ADO_PD1 70 ADI_PD0 71 CORE_VDD 72 HCKR_PC2 73 HCKT2_PC5 74 IO_GND 75 IO_VDD 76 SCKR_PC0 77 SCKT_PC3 78 FSR_PC1 79 FST_PC4 80 SDO5_SDI10_PC6 Freescale Semiconductor ...
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... Freescale Semiconductor DSP56371 Data Sheet, Rev. 4.1 Package Information 59 ...
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... Package Information 60 DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor ...
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... Freescale Semiconductor DSP56371 Data Sheet, Rev. 4.1 Package Information 61 ...
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... Package Information 62 DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor ...
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... To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. • If the temperature of the package case (T resistance is computed using the value obtained by the equation (T – Freescale Semiconductor , in °C can be obtained from the following equation × θJA R θ ...
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... RESET must be asserted when the chip is powered up. A stable EXTAL signal must be supplied before deassertion of RESET. 64 CAUTION power source to GND and GND circuits. CC and GND CCP DSP56371 Data Sheet, Rev. 4.1 , has been defined JT ). The suggested value CC pin on the DSP and from CC CC and GND. pins. P Freescale Semiconductor and ...
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... F1=low frequency (any specified operating frequency lower than F2) F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application. Freescale Semiconductor × × I ...
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... DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor ...
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... Initialise Green HLX jsr $FF1FA1 ; Disable DAX move #>$15F,x1 move x1,P:$FF0D7F ; Run Green HLX jmp $FF1FDB nop nop nop nop nop nop dor forever,endprog nop nop endprog nop Freescale Semiconductor DSP56371 Data Sheet, Rev. 4.1 Power Consumption Benchmark 67 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...