LMH1982SQEEVAL National Semiconductor, LMH1982SQEEVAL Datasheet - Page 13

• Manufacturer Part Number: LMH1982SQEEVAL
• Description: BOARD EVAL FOR LMH1982SQE
• Manufacturer: National Semiconductor

Specifications of LMH1982SQEEVAL

• Main Purpose: Video, Video Processing
• Utilized Ic / Part: LMH1982SQE
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

This panel is used to specify the input timing format and input characteristics of the selected
reference. The default values are set up for an NTSC reference timing format with negative
polarities (active low) sync input signals. Refer to the datasheet for the table of supported input
reference timing formats/standards and corresponding PLL divider register values.
If the reference signal at the HREF input is a 27 MHz clock source, select 27 MHz Clock in the
Reference Type panel; otherwise, select H sync Signal.
In the text field for Reference Divide, you can specify the value of the REF_DIV register, which
sets the denominator of the 27 MHz PLL divide ratio based on the look-up table below.
Table 3: Reference Divider Look-Up Table
In the text field for Feedback Divide, you can specify the value of the FB_DIV register, which
sets the numerator of the 27 MHz PLL divide ratio.
Using the buttons in the Sync Polarities panel, you can change the button values to specify the
pulse polarity for the HREF input and VREF input of both Reference A and B. A button value
of 0 (default) corresponds to negative polarity (active low) and a value of 1 corresponds to
positive polarity (active high).
5.3.4 Clock Output Control
This panel allows you to select the clock frequency and output mode for the SD clock output and
the HD clock output. If the clock output is not used, then you can disable the output, which sets
National Semiconductor Corp.
REF_DIV
(decimal)
value
1
0
2
REF_DIV
bit 1
0
0
1
REF_DIV
bit 0
1
0
0
Rev. 2.1, 5/13/2008
Actual PLL Reference
Divide value
(decimal)
1
2
5
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