LP2996LQEVAL National Semiconductor, LP2996LQEVAL Datasheet
LP2996LQEVAL
Specifications of LP2996LQEVAL
Related parts for LP2996LQEVAL
LP2996LQEVAL Summary of contents
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... Suspend To RAM (STR) functionality. When SD is pulled low the V state providing a high impedance output, but, V active. A power savings advantage can be obtained in this mode through lower quiescent current. Typical Application Circuit © 2011 National Semiconductor Corporation LP2996 Features ■ Source and sink current ■ ...
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Connection Diagrams Top View LLP-16 Layout SO-8 Layout Pin Descriptions SO-8 Pin or LLP Pin PSOP-8 Pin 11 14 ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. AVIN to GND PVIN to GND VDDQ (Note 2) Storage Temp. Range Junction Temperature SO-8 Thermal Resistance (θ PSOP-8 Thermal Resistance (θ LLP-16 Thermal Resistance (θ ...
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Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which the device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test ...
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Typical Performance Characteristics and REF DDQ 20057520 20057522 20057524 20057521 REF REF 20057523 OUT 20057525 ...
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DDQ Temperature IN Maximum Sourcing Current 2.5V, PV DDQ www.national.com 20057526 20057528 IN = 2.5V) IN 20057532 Temperature IN 20057527 Maximum Sourcing Current ...
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Maximum Sinking Current 2.5V) DDQ Maximum Sinking Current 1.8V) DDQ Block Diagram Maximum Sourcing Current DDQ 20057534 Maximum Sourcing Current DDQ 20057536 7 IN ...
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Description The LP2996 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2. The output, V capable of sinking and sourcing current while regulating the output voltage equal to VDDQ / 2. The output stage has ...
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Despite the fact that the LP2996 is designed to handle large transient output currents it is not capable of handling these for long durations, under all conditions. The reason ...
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Via wall thickness JA for this calculation is 0.036 mm for 1oz. Copper. FIGURE 3. LLP-16 θ Vias (4 Layer JEDEC Board)) JA Additional improvements in lowering the θ ...
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Typical Application Circuits Several different application circuits have been shown in ure 5 through Figure 14 to illustrate some of the options that are possible in configuring the LP2996. Graphs of the indi- vidual circuit performance can be found in ...
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FIGURE 7. SSTL-2 Implementation with higher voltage rails DDR-II APPLICATIONS With the separate VDDQ pin and an internal resistor divider it is possible to use the LP2996 in applications utilizing DDR- II memory. Figure 6 and Figure 7 show several ...
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LEVEL SHIFTING If standards other than SSTL-2 are required, such as SSTL-3, it may be necessary to use a different scaling factor than 0.5 times V for regulating the output voltage. Several options DDQ are available to scale the output ...
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QDR APPLICATIONS Quad data rate (QDR) applications utilize multiple channels for improved memory performance. However, this increase in bus lines has the effect of increasing the current levels re- quired for termination. The recommended approach in termi- nating multiple channels ...
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PCB Layout Considerations 1. The input capacitor for the power rail should be placed as close as possible to the PVIN pin should be connected to the V SENSE at the point where regulation is required. For motherboard ...
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Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 8-Lead Small Outline Package (M8) NS Package Number M08A 16 ...
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LLP Package (LD) NS Package Number LQA16A 8-Lead PSOP Package (PSOP-8) NS Package Number MRA08A 17 www.national.com ...
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