ATTINY20-EK1 Atmel, ATTINY20-EK1 Datasheet - Page 127
ATTINY20-EK1
Manufacturer Part Number
ATTINY20-EK1
Description
KIT EVAL TOUCH ATTINY20
Manufacturer
Atmel
Datasheet
1.ATTINY20-EK1.pdf
(224 pages)
Specifications of ATTINY20-EK1
Sensor Type
*
Sensing Range
*
Interface
*
Sensitivity
*
Voltage - Supply
*
Embedded
*
Utilized Ic / Part
*
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
TinyAVR
Kit Contents
Board
Svhc
No SVHC (15-Dec-2010)
Mcu Supported Families
ATtiny20
Tool / Board Applications
Microcontroller
Rohs Compliant
Yes
Tool Type
Development Kit
Cpu Core
AVR 8
Data Bus Width
8 bit
Processor To Be Evaluated
ATtiny20
Interface Type
Touch
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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15.13.4
8235B–AVR–04/11
ADCSRB – ADC Control and Status Register B
• Bits 2:0 – ADPS[2:0]: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input clock
to the ADC.
Table 15-5.
• Bit 7 – VDEN
This bit is reserved for QTouch, always write as zero.
• Bit 6 – VDPD
This bit is reserved for QTouch, always write as zero.
• Bits 5:4 – Res: Reserved Bits
These are reserved bits. For compatibility with future devices always write these bits to zero.
• Bit 3 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a comple the description of this bit, see
page
• Bits 2:0 – ADTS[2:0] : ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conver-
sion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a
trigger source that is cleared to a trigger source that is set, will generate a positive edge on the
Bit
0x11
Read/Write
Initial Value
125.
ADPS2
0
0
0
0
1
1
1
1
ADC Prescaler Selections
VDEN
R/W
7
0
VDPD
R/W
ADPS1
6
0
0
0
1
1
0
0
1
1
R
5
–
0
R
4
–
0
ADPS0
0
1
0
1
0
1
0
1
ADLAR
“ADCL and ADCH – ADC Data Register” on
R/W
3
0
ADTS2
R/W
2
0
ADTS1
Division Factor
R/W
1
0
128
16
32
64
2
2
4
8
ADTS0
ATtiny20
R/W
0
0
ADCSRB
127
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