STEVAL-IFS006V1 STMicroelectronics, STEVAL-IFS006V1 Datasheet - Page 69
STEVAL-IFS006V1
Manufacturer Part Number
STEVAL-IFS006V1
Description
BOARD EVAL 8BIT MICRO + TDE1708
Manufacturer
STMicroelectronics
Datasheets
1.TDE1708DFT.pdf
(14 pages)
2.STEVAL-IFS006V1.pdf
(136 pages)
3.STEVAL-IFS006V1.pdf
(4 pages)
Specifications of STEVAL-IFS006V1
Design Resources
STEVAL-IFS006V1 Bill of Material
Sensor Type
Proximity
Interface
I²C
Voltage - Supply
6 V ~ 48 V
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
ST7FLITEUS5, TDE1708
Processor To Be Evaluated
ST7LITEUS5
Data Bus Width
8 bit
Operating Supply Voltage
6 V to 48 V
Silicon Manufacturer
ST Micro
Silicon Core Number
TDE1708DFT
Kit Application Type
Sensing - Touch / Proximity
Application Sub Type
Proximity Switch
Kit Contents
Board
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Sensitivity
-
Sensing Range
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-6403
STEVAL-IFS006V1
STEVAL-IFS006V1
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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ST7LITEUS2, ST7LITEUS5
10.1.6
Register description
Lite timer control/status register (LTCSR)
Reset value: 0000 0x00 (0xh)
ICIE
7
Bit 7 ICIE Interrupt Enable.
Bit 6 ICF Input Capture Flag.
Bit 5 TB Timebase period selection.
Bit 4 TBIE Timebase Interrupt enable.
Bit 3 TBF Timebase Interrupt Flag.
ICF
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
This bit is set by hardware and cleared by software by reading the LTICR register.
Writing to this bit does not change the bit value.
0: No input capture
1: An input capture has occurred
Note: After an MCU reset, software must initialise the ICF bit by reading the LTICR
This bit is set and cleared by software.
0: Timebase period = t
1: Timebase period = t
This bit is set and cleared by software.
0: Timebase (TB) interrupt disabled
1: Timebase (TB) interrupt enabled
This bit is set by hardware and cleared by software reading the LTCSR register.
Writing to this bit has no effect.
0: No counter overflow
1: A counter overflow has occurred
register
TB
OSC
OSC
TBIE
Read / Write
* 8000 (1 ms @ 8 MHz)
* 16000 (2 ms @ 8 MHz)
TBF
WDGR
On-chip peripherals
WDGE
WDGD
0
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