DM320001 Microchip Technology, DM320001 Datasheet - Page 16

• Manufacturer Part Number: DM320001
• Description: KIT EVAL PIC32 STARTER
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DM320001

• Contents: Board, USB mini-b cable and software
• Processor To Be Evaluated: PIC 32
• Data Bus Width: 32 bit
• Interface Type: USB
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC32
• Silicon Core Number: PIC32MX
• Kit Contents: Demo Board, USB Cable, And PIC32 Starter Kit Installation CD-ROM
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC32
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC164127-5 - BOARD GRAPH LCD CNTLR PICTAILAC164127-3 - BOARD DAUGHTER GRAPHIC PICTAIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS61146B-page 12
Processor core:
• MIPS M4K with 5-stage pipeline
• MIPS32-compatible Release 2 Instruction Set
• MIPS16e™ Code Compression to improve code density by up to 40%
• GPR shadow registers to minimize latency for interrupt handlers
• Bit field manipulation instructions
• High-performance Multiply/Divide Unit:
• Static implementation: minimum operating frequency 0 MHz
• 2.3 to 3.6V operation with full speed over entire range
• Low-power modes including RUN, IDLE, and SLEEP
Memory:
• Unified 4GB virtual memory space
• Fixed Memory Mapping Translation (FMT) mechanism
• Flexible partitioning into kernel and user accessible memory segments for
Pre Fetch Cache:
• 16 lines, each 128-bit wide, instruction Prefetch buffer
• Ability to load and lock lines – useful to create SW breakpoints in Flash and
Interrupt Controller:
• Fully programmable interrupt controller with Single or Multi vector mode, support-
• Multiple priorities and subpriorities for each vector
• Highest priority interrupt has dedicated register set for reduced interrupt latency
DMA Controller:
• Up to 4 independent channels
• Memory-to-Memory, Memory-to-Peripheral, and Peripheral-to-Memory transfers
• Programmable trigger from any IRQ
• Chainable channels, stop on match detection, Auto-Enable mode
• Data transfers can occur while the core is in IDLE mode
• Integrated programmable CRC engine: calculates on the fly while the data is
Enhanced Parallel Master Port:
• 8- and 16-bit data interface
• Up to 16-bit address lines, expandable using GPIO lines
• 2 Chip Select lines
- Maximum issue rate of one 32x16 multiply per clock
- Maximum issue rate of one 32x32 multiply every other clock
increased application stability
minimize interrupt latency
ing up to 95 IRQs.
transferred.
© 2008 Microchip Technology Inc.