C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 106

DEVKIT-F120/21/22/23/24/25/26/27

C8051F120DK

Manufacturer Part Number
C8051F120DK
Description
DEVKIT-F120/21/22/23/24/25/26/27
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F120DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F12x and C8051F13x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F120
Silicon Family Name
C8051F12x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F120, 121, 122, 123, 124, 125, 126, 127
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1224

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C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
8.1.1. Update Output On-Demand
In its default mode (DAC0CN.[4:3] = ‘00’) the DAC0 output is updated “on-demand” on a write to the high-
byte of the DAC0 data register (DAC0H). It is important to note that writes to DAC0L are held, and have no
effect on the DAC0 output until a write to DAC0H takes place. If writing a full 12-bit word to the DAC data
registers, the 12-bit data word is written to the low byte (DAC0L) and high byte (DAC0H) data registers.
Data is latched into DAC0 after a write to the corresponding DAC0H register, so the write sequence
should be DAC0L followed by DAC0H if the full 12-bit resolution is required. The DAC can be used in 8-
bit mode by initializing DAC0L to the desired value (typically 0x00), and writing data to only DAC0H (also
see
Section 8.2
for information on formatting the 12-bit DAC data word within the 16-bit SFR space).
8.1.2. Update Output Based on Timer Overflow
Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow indepen-
dently of the processor, the DAC outputs can use a Timer overflow to schedule an output update event.
This feature is useful in systems where the DAC is used to generate a waveform of a defined sampling rate
by eliminating the effects of variable interrupt latency and instruction execution on the timing of the DAC
output. When the DAC0MD bits (DAC0CN.[4:3]) are set to ‘01’, ‘10’, or ‘11’, writes to both DAC data regis-
ters (DAC0L and DAC0H) are held until an associated Timer overflow event (Timer 3, Timer 4, or Timer 2,
respectively) occurs, at which time the DAC0H:DAC0L contents are copied to the DAC input latches allow-
ing the DAC output to change to the new value.
8.2.
DAC Output Scaling/Justification
In some instances, input data should be shifted prior to a DAC0 write operation to properly justify data
within the DAC input registers. This action would typically require one or more load and shift operations,
adding software overhead and slowing DAC throughput. To alleviate this problem, the data-formatting fea-
ture provides a means for the user to program the orientation of the DAC0 data word within data registers
DAC0H and DAC0L. The three DAC0DF bits (DAC0CN.[2:0]) allow the user to specify one of five data
word orientations as shown in the DAC0CN register definition.
DAC1 is functionally the same as DAC0 described above. The electrical specifications for both DAC0 and
DAC1 are given in Table 8.1.
106
Rev. 1.4

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