C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 156

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
11.3.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP-EIP2) used to configure its
priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 11.4.
11.3.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is
5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. Additional clock cycles will be required if a cache miss occurs (see
Cache” on page 211
tion is executed before an LCALL is made to service the pending interrupt. Therefore, the maximum
response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of
greater priority) is when the CPU is performing an RETI instruction followed by a DIV as the next instruc-
tion, and a cache miss event also occurs. If the CPU is executing an ISR for an interrupt with equal or
higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI
and following instruction.
156
Interrupt Source
Comparator 1 Rising Edge 0x006B
Timer 3
ADC0 End of Conversion
Timer 4
ADC2 Window Comparator 0x008B
ADC2 End of Conversion
RESERVED
UART1
for more details). If an interrupt is pending when a RETI is executed, a single instruc-
Table 11.4. Interrupt Summary (Continued)
0x007B
0x009B
0x00A3
0x0073
0x0083
0x0093
Interru
Vector
pt
Priority
Order
13
14
15
16
17
18
19
20
Pending Flags
CP1RIF (CPT1CN.5)
TF3 (TMR3CN.7)
EXF3 (TMR3CN.6)
AD0INT (ADC0CN.5)
TF4 (TMR4CN.7)
EXF4 (TMR4CN.7)
AD2WINT
(ADC2CN.0)
AD2INT (ADC2CN.5)
N/A
RI1 (SCON1.0)
TI1 (SCON1.1)
Rev. 1.4
N/A N/A N/A N/A
Y
Y
Y
Y
Y
Y
Y
Section “16. Branch Target
1
0
2
2
2
1
2
ECP1R
(EIE1.7)
Enable
Flag
ET3
(EIE2.0)
EADC0
(EIE2.1)
ET4
(EIE2.2)
EWADC2
(EIE2.3)
EADC2
(EIE2.4)
ES1
(EIE2.6)
Priority
Control
PCP1F
(EIP1.7)
PT3
(EIP2.0)
PADC0
(EIP2.1)
PT4
(EIP2.2)
PWADC2
(EIP2.3)
PADC2
(EIP2.4)
N/A
PS1
(EIP2.6)