C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 177

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

13. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
•
•
•
•
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost even though the data on the stack are not altered.
The I/O port latches are reset to 0xFF (all logic 1’s), activating internal weak pullups during and after the
reset. For V
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator running at its lowest frequency. Refer to Section “
tion on selecting and configuring the system clock source. The Watchdog Timer is enabled using its
longest timeout interval (see Section “
source is stable, program execution begins at location 0x0000.
There are seven sources for putting the MCU into the reset state: power-on, power-fail, external RST pin,
external CNVSTR0 signal, software command, Comparator0, Missing Clock Detector, and Watchdog
Timer. Each reset source is described in the following sections.
CIP-51 halts program execution.
Special Function Registers (SFRs) are initialized to their defined reset values.
External port pins are forced to a known configuration.
Interrupts and timers are disabled.
(Port
XTAL1
XTAL2
DD
I/O)
CP0+
CP0-
Monitor resets, the RST pin is driven low until the end of the V
Generator
Circuitry
Internal
Clock
OSC
Crossbar
PLL
Comparator0
CNVSTR
+
-
(CNVSTR
enable)
reset
enable)
Figure 13.1. Reset Sources
(CP0
reset
Clock Select
System
Clock
13.7. Watchdog Timer Reset
Detector
Missing
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
CIP-51
Rev. 1.4
VDD
Handler
Core
EN
WDT
C8051F120/1/2/3/4/5/6/7
PRE
Supply
Monitor
+
-
Software Reset
System Reset
14. Oscillators
Timeout
Supply
Reset
” on page
C8051F130/1/2/3
(wired-OR)
DD
179
Reset
Funnel
” on page
reset timeout.
). Once the system clock
185
/RST
for informa-
177