C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 178

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
13.1. Power-on Reset
The C8051F120/1/2/3/4/5/6/7 family incorporates a power supply monitor that holds the MCU in the reset
state until V
to Table 13.1 for the Electrical Characteristics of the power supply monitor circuit. The RST pin is asserted
low until the end of the 100 ms V
Monitor reset is enabled and disabled using the external V
Monitor is enabled, it is selected as a reset source using the PORSF bit. If the RSTSRC register is written
by firmware, PORSF (RSTSRC.1) must be written to ‘1’ for the V
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other
reset flags in the RSTSRC Register are indeterminate. PORSF is cleared by all other resets. Since all
resets cause program execution to begin at the same location (0x0000) software can read the PORSF flag
to determine if a power-up was the cause of reset. The contents of internal data memory should be
assumed to be undefined after a power-on reset.
13.2. Power-fail Reset
When a power-down transition or power irregularity causes V
monitor will drive the RST pin low and return the CIP-51 to the reset state. When V
above VRST, the CIP-51 will leave the reset state in the same manner as that for the power-on reset (see
Figure 13.2). Note that even though internal data memory contents are not altered by the power-fail reset,
it is impossible to determine if V
set to logic 1, the data may no longer be valid.
178
Logic HIGH
Logic LOW
DD
rises above the V
2.70
2.55
2.0
1.0
/RST
V
RST
DD
RST
DD
dropped below the level required for data retention. If the PORSF flag is
Monitor timeout in order to allow the V
Figure 13.2. Reset Timing
level during power-up. See Figure 13.2 for timing diagram, and refer
Power-On Reset
100ms
Rev. 1.4
DD
monitor enable pin (MONEN). When the V
DD
DD
to drop below V
Monitor to be effective.
VDD Monitor Reset
DD
supply to stabilize. The V
100ms
RST
DD
, the power supply
returns to a level
t
DD
DD