C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 212

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
The replacement algorithm is selected with the Cache Algorithm bit, CHALGM (CCH0TN.3). When
CHALGM is cleared to ‘0’, the cache will use the rebound algorithm to replace cache locations. The
rebound algorithm replaces locations in order from the beginning of cache memory to the end, and then
from the end of cache memory to the beginning. When CHALGM is set to ‘1’, the cache will use the
pseudo-random algorithm to replace cache locations. The pseudo-random algorithm uses a pseudo-ran-
dom number to determine which cache location to replace. The cache can be manually emptied by writing
a ‘1’ to the CHFLUSH bit (CCH0CN.4).
16.2. Cache and Prefetch Optimization
By default, the branch target cache is configured to provide code speed improvements for a broad range of
circumstances. In most applications, the cache control registers should be left in their reset states.
Sometimes it is desirable to optimize the execution time of a specific routine or critical timing loop. The
branch target cache includes options to exclude caching of certain types of data, as well as the ability to
pre-load and lock time-critical branch locations to optimize execution speed.
The most basic level of cache control is implemented with the Cache Miss Penalty Threshold bits, CHM-
STH (CCH0TN.1-0). If the processor is stalled during a prefetch operation for more clock cycles than the
number stored in CHMSTH, the requested data will be cached when it becomes available. The CHMSTH
bits are set to zero by default, meaning that any time the processor is stalled, the new data will be cached.
If, for example, CHMSTH is equal to 2, any cache miss causing a delay of 3 or 4 clock cycles will be
cached, while a cache miss causing a delay of 1-2 clock cycles will not be cached.
212
Prefetch Data
Cache Data
A16
TAG = 15 MSBs of Absolute FLASH Address
Figure 16.2. Branch Target Cache Organiztion
Valid
V58
V59
V60
V61
V62
Bit
VL
V0
V1
V2
LINEAR TAG
Address
TAG 58
TAG 59
TAG 60
TAG 61
TAG 62
TAG 0
TAG 1
TAG 2
Rev. 1.4
A2
A1 A0
0
0
1
1
LINEAR SLOT
0
1
0
1
SLOT 58
SLOT 59
SLOT 60
SLOT 61
SLOT 62
SLOT 0
SLOT 1
SLOT 2
Data
SLOT = 4 Instruction
Data Bytes
Byte 0
Byte 1
Byte 2
Byte 3