C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 253

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
The output modes of the Port pins on Ports 4 through 7 are determined by the bits in their respective
PnMDOUT Output Mode Registers. Each bit in PnMDOUT controls the output mode of its corresponding
port pin (see SFR Definition 18.14, SFR Definition 18.16, SFR Definition 18.18, and SFR Definition 18.20).
For example, to place Port pin 4.3 in push-pull mode (digital output), set P4MDOUT.3 to logic 1. All port
pins default to open-drain mode upon device reset.
18.2.3. Configuring Port Pins as Digital Inputs
A Port pin is configured as a digital input by setting its output mode to “Open-Drain” and writing a logic 1 to
the associated bit in the Port Data register. For example, P7.7 is configured as a digital input by setting
P7MDOUT.7 to a logic 0 and P7.7 to a logic 1.
18.2.4. Weak Pullups
By default, each Port pin has an internal weak pullup device enabled which provides a resistive connection
(about 100 k  ) between the pin and V
. The weak pullup devices can be globally disabled by writing a
DD
logic 1 to the Weak Pullup Disable bit, (WEAKPUD, XBR2.7). The weak pullup is automatically deactivated
on any pin that is driving a logic 0; that is, an output pin will not contend with its own pullup device.
18.2.5. External Memory Interface
If the External Memory Interface (EMIF) is enabled on the High ports (Ports 4 through 7), EMIFLE
(XBR2.5) should be set to a logic 0.
If the External Memory Interface is enabled on the High ports and an off-chip MOVX operation occurs, the
External Memory Interface will control the output states of the affected Port pins during the execution
phase of the MOVX instruction, regardless of the settings of the Port Data registers. The output configura-
tion of the Port pins is not affected by the EMIF operation, except that Read operations will explicitly dis-
able the output drivers on the Data Bus during the MOVX execution. See
Section “17. External Data
Memory Interface and On-Chip XRAM” on page 219
for more information about the External Memory
Interface.
Rev. 1.4
253