C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 263

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

19.3.3. Slave Transmitter Mode
Serial data is transmitted on SDA while the serial clock is received on SCL. The SMBus0 interface receives
a START followed by data byte containing the slave address and direction bit. If the received slave address
matches the address held in register SMB0ADR, the SMBus0 interface generates an ACK. SMBus0 will
also ACK if the general call address (0x00) is received and the General Call Address Enable bit
(SMB0ADR.0) is set to logic 1. In this case the data direction bit (R/W) will be logic 1 to indicate a "READ"
operation. The SMBus0 interface receives the clock on SCL and transmits one or more bytes of serial
data, waiting for an ACK from the master after each byte. SMBus0 exits slave mode after receiving a
STOP condition from the master.
19.3.4. Slave Receiver Mode
Serial data is received on SDA while the serial clock is received on SCL. The SMBus0 interface receives a
START followed by data byte containing the slave address and direction bit. If the received slave address
matches the address held in register SMB0ADR, the interface generates an ACK. SMBus0 will also ACK if
the general call address (0x00) is received and the General Call Address Enable bit (SMB0ADR.0) is set to
logic 1. In this case the data direction bit (R/W) will be logic 0 to indicate a "WRITE" operation. The
SMBus0 interface receives one or more bytes of serial data; after each byte is received, the interface
transmits an ACK or NACK depending on the state of the AA bit in SMB0CN. SMBus0 exits Slave Receiver
Mode after receiving a STOP condition from the master.
S
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 19.6. Typical Slave Transmitter Sequence
Figure 19.7. Typical Slave Receiver Sequence
SLA
SLA
Interrupt
W
R
Interrupt
A
A
Data Byte
Data Byte
Rev. 1.4
C8051F120/1/2/3/4/5/6/7
Interrupt
Interrupt
A
A
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address
Data Byte
Data Byte
C8051F130/1/2/3
Interrupt
Interrupt
A
N
Interrupt
Interrupt
P
P
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