C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 298
C8051F120DK
Manufacturer Part Number
C8051F120DK
Description
DEVKIT-F120/21/22/23/24/25/26/27
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F120DK.pdf
(350 pages)
Specifications of C8051F120DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F12x and C8051F13x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F120
Silicon Family Name
C8051F12x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F120, 121, 122, 123, 124, 125, 126, 127
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1224
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F120DK
Manufacturer:
SiliconL
Quantity:
4
- Current page: 298 of 350
- Download datasheet (2Mb)
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
298
Bits7–0: SADDR0.[7:0]: UART0 Slave Address
Bits7–0: SADEN0.[7:0]: UART0 Slave Address Enable
Bits7–0: SBUF0.[7:0]: UART0 Buffer Bits 7–0 (MSB–LSB)
R/W
R/W
R/W
Bit7
Bit7
Bit7
The contents of this register are used to define the UART0 slave address. Register SADEN0
is a bit mask to determine which bits of SADDR0 are checked against a received address:
corresponding bits set to logic 1 in SADEN0 are checked; corresponding bits set to logic 0
are “don’t cares”.
Bits in this register enable corresponding bits in register SADDR0 to determine the UART0
slave address.
0: Corresponding bit in SADDR0 is a “don’t care”.
1: Corresponding bit in SADDR0 is checked against a received address.
This is actually two registers; a transmit and a receive buffer register. When data is moved
to SBUF0, it goes to the transmit buffer and is held for serial transmission. Moving a byte to
SBUF0 is what initiates the transmission. When data is moved from SBUF0, it comes from
the receive buffer.
SFR Definition 21.5. SADEN0: UART0 Slave Address Enable
R/W
R/W
R/W
Bit6
Bit6
Bit6
SFR Definition 21.4. SADDR0: UART0 Slave Address
SFR Definition 21.3. SBUF0: UART0 Data Buffer
R/W
R/W
R/W
Bit5
Bit5
Bit5
R/W
R/W
Bit4
Bit4
R/W
Bit4
Rev. 1.4
R/W
R/W
Bit3
Bit3
R/W
Bit3
R/W
R/W
Bit2
Bit2
R/W
Bit2
R/W
R/W
R/W
Bit1
Bit1
Bit1
SFR Address:
SFR Address:
SFR Address:
SFR Page:
SFR Page:
SFR Page:
R/W
R/W
Bit0
Bit0
R/W
Bit0
0xB9
0
0xA9
0
00000000
Reset Value
0x99
0
00000000
Reset Value
00000000
Reset Value
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