C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 301

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

22.2. Operational Modes
UART1 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S1MODE bit (SCON1.7). Typical UART connection options are shown below.
22.2.1. 8-Bit UART
8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop
bit. Data are transmitted LSB first from the TX1 pin and received at the RX1 pin. On receive, the eight data
bits are stored in SBUF1 and the stop bit goes into RB81 (SCON1.2).
Data transmission begins when software writes a data byte to the SBUF1 register. The TI1 Transmit Inter-
rupt Flag (SCON1.1) is set at the end of the transmission (the beginning of the stop-bit time). Data recep-
tion can begin any time after the REN1 Receive Enable bit (SCON1.4) is set to logic 1. After the stop bit is
received, the data byte will be loaded into the SBUF1 receive register if the following conditions are met:
RI1 must be logic 0, and if MCE1 is logic 1, the stop bit must be logic 1. In the event of a receive data over-
run, the first received 8 bits are latched into the SBUF1 receive register and the following overrun data bits
are lost.
If these conditions are met, the eight bits of data is stored in SBUF1, the stop bit is stored in RB81 and the
RI1 flag is set. If these conditions are not met, SBUF1 and RB81 will not be loaded and the RI1 flag will not
be set. An interrupt will occur if enabled when either TI1 or RI1 is set.
SPACE
MARK
BIT TIMES
BIT SAMPLING
START
BIT
Figure 22.3. UART Interconnect Diagram
Figure 22.4. 8-Bit UART Timing Diagram
D0
RS-232
D1
MCU
D2
RX
TX
Rev. 1.4
D3
RS-232
LEVEL
XLTR
OR
C8051F120/1/2/3/4/5/6/7
D4
RX
RX
TX
TX
C8051Fxxx
D5
C8051Fxxx
C8051F130/1/2/3
D6
D7
STOP
BIT
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