C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 317

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
23.2. Timer 2, Timer 3, and Timer 4
Timers 2, 3, and 4 are 16-bit counter/timers, each formed by two 8-bit SFR’s: TMRnL (low byte) and
TMRnH (high byte) where n = 2, 3, and 4 for timers 2, 3, and 4 respectively. Timers 2 and 4 feature auto-
reload, capture, and toggle output modes with the ability to count up or down. Timer 3 features auto-reload
and capture modes, with the ability to count up or down. Capture Mode and Auto-reload mode are selected
using bits in the Timer 2, 3, and 4 Control registers (TMRnCN). Toggle output mode is selected using the
Timer 2 or 4 Configuration registers (TMRnCF). These timers may also be used to generate a square-
wave at an external pin. As with Timers 0 and 1, Timers 2, 3, and 4 can use either the system clock
(divided by one, two, or twelve), external clock (divided by eight) or transitions on an external input pin as
its clock source. Timer 2 and 3 can be used to start an ADC Data Conversion and Timers 2, 3, and 4 can
schedule DAC outputs. Timers 1, 2, 3, or 4 may be used to generate baud rates for UART 0. Only Timer 1
can be used to generate baud rates for UART 1.
The Counter/Timer Select bit C/Tn bit (TMRnCN.1) configures the peripheral as a counter or timer. Clear-
ing C/Tn configures the Timer to be in a timer mode (i.e., the system clock or transitions on an external pin
as the input for the timer). When C/Tn is set to 1, the timer is configured as a counter (i.e., high-to-low tran-
sitions at the Tn input pin increment (or decrement) the counter/timer register. Timer 3 and Timer 2 share
the T2 input pin. Refer to
Section “18.1. Ports 0 through 3 and the Priority Crossbar Decoder” on
page 238
for information on selecting and configuring external I/O pins for digital peripherals, such as the
Tn pin.
Timer 2, 3, and 4 can use either SYSCLK, SYSCLK divided by 2, SYSCLK divided by 12, an external clock
divided by 8, or high-to-low transitions on the Tn input pin as its clock source when operating in Counter/
Timer with Capture mode. Clearing the C/Tn bit (TMRnCN.1) selects the system clock/external clock as
the input for the timer. The Timer Clock Select bits TnM0 and TnM1 in TMRnCF can be used to select the
system clock undivided, system clock divided by two, system clock divided by 12, or an external clock pro-
vided at the XTAL1/XTAL2 pins divided by 8 (see SFR Definition 23.13). When C/Tn is set to logic 1, a
high-to-low transition at the Tn input pin increments the counter/timer register (i.e., configured as a coun-
ter).
23.2.1. Configuring Timer 2, 3, and 4 to Count Down
Timers 2, 3, and 4 have the ability to count down. When the timer’s Decrement Enable Bit (DCENn) in the
Timer Configuration Register (See SFR Definition 23.13) is set to ‘1’, the timer can then count up or down .
When DCENn = 1, the direction of the timer’s count is controlled by the TnEX pin’s logic level (Timer 3
shares the T2EX pin with Timer 2). When TnEX = 1, the counter/timer will count up; when TnEX = 0, the
counter/timer will count down. To use this feature, TnEX must be enabled in the digital crossbar and config-
ured as a digital input.
Note: When DCENn = 1, other functions of the TnEX input (i.e., capture and auto-reload) are not
available. TnEX will only control the direction of the timer when DCENn = 1.
Rev. 1.4
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