C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 91

DEVKIT-F120/21/22/23/24/25/26/27

C8051F120DK

Manufacturer Part Number
C8051F120DK
Description
DEVKIT-F120/21/22/23/24/25/26/27
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F120DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F12x and C8051F13x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F120
Silicon Family Name
C8051F12x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F120, 121, 122, 123, 124, 125, 126, 127
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1224

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7.
The C8051F12x devices include a second ADC peripheral (ADC2), which consists of an 8-channel, config-
urable analog multiplexer, a programmable gain amplifier, and a 500 ksps, 8-bit successive-approximation-
register ADC with integrated track-and-hold (see block diagram in Figure 7.1). ADC2 is fully configurable
under software control via the Special Function Registers shown in Figure 7.1. The ADC2 subsystem (8-bit
ADC, track-and-hold and PGA) is enabled only when the AD2EN bit in the ADC2 Control register
(ADC2CN) is set to logic 1. The ADC2 subsystem is in low power shutdown when this bit is logic 0. The
voltage reference used by ADC2 is selected as described in
page 113
7.1.
Eight ADC2 channels are available for measurement, as selected by the AMX2SL register (see SFR Defi-
nition 7.2). The PGA amplifies the ADC2 output signal by an amount determined by the states of the
AMP2GN2-0 bits in the ADC2 Configuration register, ADC2CF (SFR Definition 7.3). The PGA can be soft-
ware-programmed for gains of 0.5, 1, 2, or 4. Gain defaults to 0.5 on reset.
Important Note : AIN2 pins also function as Port 1 I/O pins, and must be configured as analog inputs when
used as ADC2 inputs. To configure an AIN2 pin for analog input, set to ‘0’ the corresponding bit in register
P1MDIN. Port 1 pins selected as analog inputs are skipped by the Digital I/O Crossbar. See
“18.1.5. Configuring Port 1 Pins as Analog Inputs” on page 240
the AIN2 pins.
AIN2.0 (P1.0)
AIN2.1 (P1.1)
AIN2.2 (P1.2)
AIN2.3 (P1.3)
AIN2.4 (P1.4)
AIN2.5 (P1.5)
AIN2.6 (P1.6)
AIN2.7 (P1.7)
ADC2 (8-Bit ADC, C8051F12x Only)
Analog Multiplexer and PGA
.
AMX2CF
Figure 7.1. ADC2 Functional Block Diagram
+
+
+
+
-
-
-
-
AMUX
8-to-1
AMX2SL
X
+
-
AV+
AD2EN
ADC2GTH
AGND
Rev. 1.4
ADC2CF
C8051F120/1/2/3/4/5/6/7
ADC
8-Bit
SAR
AV+
ADC2CN
ADC2LTH
Section “9. Voltage Reference” on
for more information on configuring
C8051F130/1/2/3
Start Conversion
8
8
000
001
010
011
1xx
8
16
Write to AD2BUSY
Timer 3 Overflow
CNVSTR2
Timer 2 Overflow
Write to AD0BUSY
(synchronized with
ADC0)
Comp
Dig
AD2WINT
Section
91

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