C8051F330DK Silicon Laboratories Inc, C8051F330DK Datasheet - Page 121

• Manufacturer Part Number: C8051F330DK
• Description: DEV KIT FOR C8051F330/F331
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F330DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F33x
• Interface Type: RS-232
• Operating Supply Voltage: 7 V to 15 V
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F330
• Silicon Family Name: C8051F33x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F330, C8051F331
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1264

14.1. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 14.3) assigns a priority to each I/O function, starting at the top with
UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that
resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips
that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose
associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that
are to be used for analog input, dedicated functions, or GPIO.
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding PnSKIP bit should be set. This applies to P0.0 if VREF is used, P0.3 and/or
P0.2 if the external oscillator circuit is enabled, P0.6 if the ADC or IDAC is configured to use the external
conversion start signal (CNVSTR), and any selected ADC or Comparator inputs. The Crossbar skips
selected pins as if they were already assigned, and moves to the next unassigned pin. Figure 14.3 shows
the Crossbar Decoder priority with no Port pins skipped (P0SKIP, P1SKIP = 0x00); Figure 14.4 shows the
Crossbar Decoder priority with the XTAL1 (P0.2) and XTAL2 (P0.3) pins skipped (P0SKIP = 0x0C).
SF Signals
PIN I/O
TX0
RX0
SCK
MISO
MOSI
NSS*
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
SF Signals
Figure 14.3. Crossbar Priority Decoder with No Pins Skipped
VREF IDA
Port pin potentially available to peripheral
Special Function Signals are not assigned by the crossbar.
When these signals are enabled, the CrossBar must be
manually configured to skip their corresponding port pins.
0
0
1
0
x1
2
0
P0SKIP[0:7]
x2
3
0
P0
4
0
*NSS is only pinned out in 4-wire SPI Mode
5
0
CNVSTR
Rev. 1.7
6
0
7
0
0
0
C8051F330/1/2/3/4/5
1
0
2
0
P1SKIP[0:7]
3
0
P1
4
0
5
0
6
0
7
0
P2
0
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