C8051F330DK Silicon Laboratories Inc, C8051F330DK Datasheet - Page 124

DEV KIT FOR C8051F330/F331

C8051F330DK

Manufacturer Part Number
C8051F330DK
Description
DEV KIT FOR C8051F330/F331
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F330DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F33x
Interface Type
RS-232
Operating Supply Voltage
7 V to 15 V
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F330
Silicon Family Name
C8051F33x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051F330, C8051F331
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1264
C8051F330/1/2/3/4/5
128
Bits7–6: UNUSED. Read = 00b, Write = don’t care.
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Bit7
R
-
CP0AE: Comparator0 Asynchronous Output Enable
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
CP0E: Comparator0 Output Enable
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
SYSCKE: /SYSCLK Output Enable
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK output routed to Port pin.
SMB0E: SMBus I/O Enable
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
SPI0E: SPI I/O Enable
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO pins.
URT0E: UART I/O Output Enable
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.
SFR Definition 14.1. XBR0: Port I/O Crossbar Register 0
Bit6
R
-
CP0AE
R/W
Bit5
CP0E
R/W
Bit4
SYSCKE
Rev. 1.7
R/W
Bit3
SMB0E
R/W
Bit2
SPI0E
R/W
Bit1
URT0E
R/W
Bit0
SFR Address:
00000000
Reset Value
0xE1

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