C8051F330DK Silicon Laboratories Inc, C8051F330DK Datasheet - Page 138

• Manufacturer Part Number: C8051F330DK
• Description: DEV KIT FOR C8051F330/F331
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F330DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F33x
• Interface Type: RS-232
• Operating Supply Voltage: 7 V to 15 V
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F330
• Silicon Family Name: C8051F33x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F330, C8051F331
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1264

C8051F330/1/2/3/4/5
142
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bits1–0: SMBCS1–SMBCS0: SMBus Clock Source Selection.
ENSMB
R/W
Bit7
ENSMB: SMBus Enable.
This bit enables/disables the SMBus interface. When enabled, the interface constantly mon-
itors the SDA and SCL pins.
0: SMBus interface disabled.
1: SMBus interface enabled.
INH: SMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave events
occur. This effectively removes the SMBus slave from the bus. Master Mode interrupts are
not affected.
0: SMBus Slave Mode enabled.
1: SMBus Slave Mode inhibited.
BUSY: SMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to logic 0
when a STOP or free-timeout is sensed.
EXTHOLD: SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to .
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
SMBTOE: SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces Timer 3 to
reload while SCL is high and allows Timer 3 to count when SCL goes low. If Timer 3 is con-
figured to Split Mode, only the High Byte of the timer is held in reload while SCL is high.
Timer 3 should be programmed to generate interrupts at 25 ms, and the Timer 3 interrupt
service routine should reset SMBus communication.
SMBFTE: SMBus Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high for
more than 10 SMBus clock source periods.
These two bits select the SMBus clock source, which is used to generate the SMBus bit
rate. The selected device should be configured according to Equation 15.1.
SMBCS1
SFR Definition 15.1. SMB0CF: SMBus Clock/Configuration
INH
R/W
Bit6
0
0
1
1
SMBCS0
BUSY
Bit5
R
0
1
0
1
EXTHOLD SMBTOE SMBFTE SMBCS1
R/W
Bit4
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
SMBus Clock Source
Timer 0 Overflow
Timer 1 Overflow
Rev. 1.7
R/W
Bit3
R/W
Bit2
R/W
Bit1
SFR Address:
SMBCS0 00000000
R/W
Bit0
0xC1
Reset Value