C8051F330DK Silicon Laboratories Inc, C8051F330DK Datasheet - Page 187

• Manufacturer Part Number: C8051F330DK
• Description: DEV KIT FOR C8051F330/F331
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F330DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F33x
• Interface Type: RS-232
• Operating Supply Voltage: 7 V to 15 V
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F330
• Silicon Family Name: C8051F33x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F330, C8051F331
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1264

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
TF3H
R/W
Bit7
TF3H: Timer 3 High Byte Overflow Flag.
Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit mode,
this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the Timer 3 interrupt is
enabled, setting this bit causes the CPU to vector to the Timer 3 interrupt service routine.
TF3H is not automatically cleared by hardware and must be cleared by software.
TF3L: Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. When this bit is
set, an interrupt will be generated if TF3LEN is set and Timer 3 interrupts are enabled. TF3L
will set when the low byte overflows regardless of the Timer 3 mode. This bit is not automat-
ically cleared by hardware.
TF3LEN: Timer 3 Low Byte Interrupt Enable.
This bit enables/disables Timer 3 Low Byte interrupts. If TF3LEN is set and Timer 3 inter-
rupts are enabled, an interrupt will be generated when the low byte of Timer 3 overflows.
0: Timer 3 Low Byte interrupts disabled.
1: Timer 3 Low Byte interrupts enabled.
TF3CEN: Timer 3 Low-Frequency Oscillator Capture Enable.
This bit enables/disables Timer 3 Low-Frequency Oscillator Capture Mode. If TF3CEN is set
and Timer 3 interrupts are enabled, an interrupt will be generated on a rising edge of the
low-frequency oscillator output, and the current 16-bit timer value in TMR3H:TMR3L will be
copied to TMR3RLH:TMR3RLL. See
details.
0: Timer 3 Low-Frequency Oscillator Capture disabled.
1: Timer 3 Low-Frequency Oscillator Capture enabled.
T3SPLIT: Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
0: Timer 3 operates in 16-bit auto-reload mode.
1: Timer 3 operates as two 8-bit auto-reload timers.
TR3: Timer 3 Run Control.
This bit enables/disables Timer 3. In 8-bit mode, this bit enables/disables TMR3H only;
TMR3L is always enabled in this mode.
0: Timer 3 disabled.
1: Timer 3 enabled.
UNUSED. Read = 0b. Write = don’t care.
T3XCLK: Timer 3 External Clock Select.
This bit selects the external clock source for Timer 3. If Timer 3 is in 8-bit mode, this bit
selects the external oscillator clock source for both timer bytes. However, the Timer 3 Clock
Select bits (T3MH and T3ML in register CKCON) may still be used to select between the
external clock and the system clock for either timer.
0: Timer 3 external clock selection is the system clock divided by 12.
1: Timer 3 external clock selection is the external clock divided by 8. Note that the external
oscillator source divided by 8 is synchronized with the system clock.
TF3L
R/W
Bit6
SFR Definition 18.13. TMR3CN: Timer 3 Control
TF3LEN
R/W
Bit5
TF3CEN
R/W
Bit4
T3SPLIT
Rev. 1.7
Section “13. Oscillators” on page 113
R/W
Bit3
TR3
R/W
Bit2
C8051F330/1/2/3/4/5
Bit1
—
R
T3XCLK
R/W
Bit0
for more
SFR Address:
00000000
Reset Value
0x91
191