C8051F330DK Silicon Laboratories Inc, C8051F330DK Datasheet - Page 51

• Manufacturer Part Number: C8051F330DK
• Description: DEV KIT FOR C8051F330/F331
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F330DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F33x
• Interface Type: RS-232
• Operating Supply Voltage: 7 V to 15 V
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F330
• Silicon Family Name: C8051F33x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F330, C8051F331
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1264

C8051F330/1/2/3/4/5
5.4.2. Window Detector In Differential Mode
Figure 5.7 shows two example window comparisons for right-justified, differential data, with
ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (–1d). In differential mode, the
measurable voltage between the input pins is between –VREF and VREF x (511/512). Output codes are
represented as 10-bit 2s complement signed integers. In the left example, an AD0WINT interrupt will be
generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by
ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL (if 0xFFFF (–1d) < ADC0H:ADC0L < 0x0040 (64d)). In the
right example, an AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range
defined
ADC0H:ADC0L > 0x0040 (+64d)). Figure 5.8 shows an example using left-justified data with the same
comparison values.
54
VREF x (511/512)
VREF x (511/512)
VREF x (64/512)
VREF x (64/512)
VREF x (-1/512)
Figure 5.7. ADC Window Compare Example: Right-Justified Differential Data
VREF x (-1/512)
Input Voltage
Input Voltage
Figure 5.8. ADC Window Compare Example: Left-Justified Differential Data
(Px.x - Px.x)
(Px.x - Px.x)
-VREF
-VREF
by
the
ADC0H:ADC0L
ADC0H:ADC0L
0xFFFF
0xFFFE
0x7FC0
0x0FC0
0xFFC0
0x01FF
0x0041
0x0040
0x003F
0x0000
0x0200
0x1040
0x1000
0x0000
0xFF80
0x8000
ADC0GT
ADC0GTH:ADC0GTL
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
ADC0LTH:ADC0LTL
and
not affected
not affected
not affected
not affected
AD0WINT
AD0WINT
AD0WINT
AD0WINT
ADC0LT
AD0WINT=1
AD0WINT=1
Rev. 1.7
registers
VREF x (511/512)
VREF x (511/512)
VREF x (64/512)
VREF x (64/512)
VREF x (-1/512)
VREF x (-1/512)
Input Voltage
Input Voltage
(Px.x - Px.x)
(Px.x - Px.y)
-VREF
-VREF
(if ADC0H:ADC0L < 0xFFFF
ADC0H:ADC0L
ADC0H:ADC0L
0xFFFF
0xFFFE
0x7FC0
0x0FC0
0xFFC0
0x01FF
0x0041
0x0040
0x003F
0x0000
0x0200
0x1040
0x1000
0x0000
0xFF80
0x8000
ADC0GTH:ADC0GTL
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
ADC0LTH:ADC0LTL
not affected
not affected
AD0WINT
AD0WINT
AD0WINT=1
AD0WINT=1
AD0WINT=1
AD0WINT=1
(–1d)
or