C8051F330DK Silicon Laboratories Inc, C8051F330DK Datasheet - Page 96

DEV KIT FOR C8051F330/F331

C8051F330DK

Manufacturer Part Number
C8051F330DK
Description
DEV KIT FOR C8051F330/F331
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F330DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F33x
Interface Type
RS-232
Operating Supply Voltage
7 V to 15 V
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F330
Silicon Family Name
C8051F33x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051F330, C8051F331
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1264
Important Note: The V
V
dure for configuring the V
See Figure 10.2 for V
See Table 10.1 for complete electrical characteristics of the V
10.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 10.1 for complete RST pin
specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
10.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise,
this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables
it. The state of the RST pin is unaffected by this reset.
DD
Bit7:
Bit6:
Bits5–0: Reserved. Read = 000000b. Write = don’t care.
VDMEN
monitor as a reset source before it is enabled and stabilized may cause a system reset. The proce-
R/W
Bit7
Step 1. Enable the V
Step 2. Wait for the V
Step 3. Select the V
VDMEN: V
This bit turns the V
until it is also selected as a reset source in register RSTSRC (SFR Definition 10.2). The V
Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the
V
See Table 10.1 for the minimum V
0: V
1: V
V
This bit indicates the current power supply status (V
0: V
1: V
DD
DD
VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved
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DD
DD
DD
monitor as a reset source before it has stabilized may generate a system reset.
STAT: V
Bit6
R
Monitor Disabled.
Monitor Enabled.
is at or below the V
is above the V
SFR Definition 10.1. VDM0CN: V
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DD
DD
monitor timing; note that the reset delay is not incurred after a V
DD
DD
Monitor Enable.
monitor must be enabled before it is selected as a reset source. Selecting the
Status.
monitor as a reset source is shown below:
DD
DD
Bit5
DD
R
DD
monitor as a reset source (PORSF bit in RSTSRC = ‘1’).
monitor (VDMEN bit in VDM0CN = ‘1’).
monitor to stabilize (see Table 10.1 for the V
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monitor circuit on/off. The V
monitor threshold.
DD
Bit4
R
monitor threshold.
DD
Rev. 1.7
Monitor turn-on time.
Bit3
R
DD
DD
DD
C8051F330/1/2/3/4/5
Bit2
DD
R
monitor.
Monitor cannot generate system resets
Monitor Control
Monitor output).
Bit1
R
DD
Monitor turn-on time).
SFR Address:
Bit0
R
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monitor reset.
0xFF
Reset Value
Variable
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99

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