C8051F005DK Silicon Laboratories Inc, C8051F005DK Datasheet - Page 104

• Manufacturer Part Number: C8051F005DK
• Description: DEV KIT FOR F005/006/007
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F005DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F01x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F005
• Silicon Family Name: C8051F00x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F005/006/007
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1188

not affect the push-pull Port I/O. Furthermore, the weak pullup is turned off on an open-drain output that is driving
a 0 to avoid unnecessary power dissipation.
The third and final step is to initialize the individual resources selected using the appropriate setup registers.
Initialization procedures for the various digital resources may be found in the detailed explanation of each available
function. The reset state of each register is shown in the figures that describe each individual register.
Highest
Lowest
Priority
Priority
Latches
Port
WEAKPUD
PUSH-PULL
/PORT-OUTENABLE
PORT-OUTPUT
PORT-INPUT
T0, T1, T2,
T2EX,
/INT0,
/INT1
/SYSCLK
CNVSTR
Comptr.
Outputs
SMBus
UART
P0
P1
P2
P3
PCA
SPI
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
(P3.0-P3.7)
Figure 15.1. Port I/O Functional Block Diagram
8
8
8
8
2
4
2
6
2
6
Figure 15.2. Port I/O Cell Block Diagram
XBR2 Registers
XBR0, XBR1,
Rev. 1.7
Crossbar
Decoder
Priority
Digital
VDD
8
8
8
PRT0CF, PRT1CF,
PRT2CF Registers
PRT3CF
Register
DGND
Cells
Cells
Cells
Cells
VDD
I/O
I/O
I/O
I/O
P0
P1
P2
P3
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
VDD
(WEAK)
External
Pins
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
PORT
PAD
Highest
Priority
Lowest
Priority
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