C8051F005DK Silicon Laboratories Inc, C8051F005DK Datasheet - Page 116

• Manufacturer Part Number: C8051F005DK
• Description: DEV KIT FOR F005/006/007
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F005DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F01x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F005
• Silicon Family Name: C8051F00x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F005/006/007
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1188

16.2.4. Slave Receiver Mode
Serial data is received on SDA while the serial clock is received on SCL. First, a byte is received that contains an
address and data direction bit. In this case the data direction bit (R/W) will be logic 0 to indicate a “WRITE”
operation. If the received address matches the slave’s assigned address (or a general call address is received) one or
more bytes of serial data are received from the master. After each byte is received, an acknowledge bit is
transmitted by the slave. The master outputs START and STOP conditions to indicate the beginning and end of the
serial transfer.
16.3.
A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL and
SDA lines remains high for a specified time. Two or more master devices may attempt to generate a START
condition at the same time. Since the devices that generated the START condition may not be aware that other
masters are contending for the bus, an arbitration scheme is employed. The master devices continue to transmit
until one of the masters transmits a HIGH level, while the other(s) master transmits a LOW level on SDA. The first
master(s) transmitting the HIGH level on SDA looses the arbitration and is required to give up the bus.
16.4.
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed
capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave
devices to communicate with faster masters. The slave can hold the SCL line LOW to extend the clock low period,
effectively decreasing the serial clock frequency.
16.5.
16.5.1. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the
master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol
specifies that devices participating in a transfer must detect any clock cycle held low longer than 25ms as a
“timeout” condition. Devices that have detected the timeout condition must reset the communication no later than
10ms after detecting the timeout condition.
One of the MCU’s general-purpose timers, operating in 16-bit auto-reload mode, can be used to monitor the SCL
line for this timeout condition. Timer 3 is specifically designed for this purpose. (Refer to the Timer 3 Section
19.3. for detailed information on Timer 3 operation.)
16.5.2. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if a device holds the SCL and SDA lines high for more that 50usec, the bus
is designated as free. The SMB0CR register is used to detect this condition when the FTE bit in SMB0CN is set.
16.6.
The SMBus serial interface is accessed and controlled through five SFRs: SMB0CN Control Register, SMB0CR
Clock Rate Register, SMB0ADR Address Register, SMB0DAT Data Register and SMB0STA Status Register. The
system device may have one or more SMBus serial interfaces implemented. The five special function registers
related to the operation of the SMBus interface are described in the following section.
Arbitration
Clock Low Extension
Timeouts
SMBus Special Function Registers
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
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