C8051F005DK Silicon Laboratories Inc, C8051F005DK Datasheet - Page 94

• Manufacturer Part Number: C8051F005DK
• Description: DEV KIT FOR F005/006/007
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F005DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F01x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F005
• Silicon Family Name: C8051F00x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F005/006/007
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1188

13.1.
The C8051F000 family incorporates a power supply monitor that holds the MCU in the reset state until VDD rises
above the V
Electrical Characteristics of the power supply monitor circuit.) The /RST pin is asserted (low) until the end of the
100ms VDD Monitor timeout in order to allow the VDD supply to become stable.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other reset
flags in the RSTSRC Register are indeterminate. PORSF is cleared by a reset from any other source. Since all
resets cause program execution to begin at the same location (0x0000), software can read the PORSF flag to
determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be
undefined after a power-on reset.
13.2.
Writing a 1 to the PORSF bit forces a Power-On Reset as described in Section 13.1.
13.3.
When a power-down transition or power irregularity causes VDD to drop below V
will drive the /RST pin low and return the CIP-51 to the reset state (see Figure 13.2). When VDD returns to a level
above V
though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD
dropped below the level required for data retention. If the PORSF flag is set, the data may no longer be valid.
Logic HIGH
Logic LOW
RST
Power-on Reset
Software Forced Reset
Power-fail Reset
, the CIP-51 will leave the reset state in the same manner as that for the power-on reset. Note that even
2.70
2.40
RST
2.0
1.0
level during power-up. (See Figure 13.2 for timing diagram, and refer to Table 13.1 for the
/RST
Figure 13.2. VDD Monitor Timing Diagram
V
RST
100ms
Rev. 1.7
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
RST
, the power supply monitor
100ms
t
94