C8051F005DK Silicon Laboratories Inc, C8051F005DK Datasheet - Page 97

• Manufacturer Part Number: C8051F005DK
• Description: DEV KIT FOR F005/006/007
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F005DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F01x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F005
• Silicon Family Name: C8051F00x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F005/006/007
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1188

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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
JTAGRST
(Note: Do not use read-modify-write operations on this register.)
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Bit7
R
0: JTAG is not currently in reset state.
1: JTAG is in reset state.
CNVRSEF: Convert Start Reset Source Enable and Flag
Write
0: CNVSTR is not a reset source
1: CNVSTR is a reset source (active low)
Read
0: Source of prior reset was not from CNVSTR
1: Source of prior reset was from CNVSTR
Write
0: Comparator 0 is not a reset source
1: Comparator 0 is a reset source (active low)
Read
Note: The value read from C0RSEF is not defined if Comparator 0 has not been enabled as
a reset source.
0: Source of prior reset was not from Comparator 0
1: Source of prior reset was from Comparator 0
Write
0: No Effect
1: Forces an internal reset. /RST pin is not effected.
Read
0: Prior reset source was not from write to the SWRSF bit.
1: Prior reset source was from write to the SWRSF bit.
WDTRSF: Watchdog Timer Reset Flag
0: Source of prior reset was not from WDT timeout.
1: Source of prior reset was from WDT timeout.
MCDRSF: Missing Clock Detector Flag
0: Source of prior reset was not from Missing Clock Detector timeout.
1: Source of prior reset was from Missing Clock Detector timeout.
Write
0: No effect
1: Forces a Power-On Reset. /RST is driven low.
Read
0: Source of prior reset was not from POR.
1: Source of prior reset was from POR.
0: Source of prior reset was not from /RST pin.
1: Source of prior reset was from /RST pin.
JTAGRST. JTAG Reset Flag.
C0RSEF: Comparator 0 Reset Enable and Flag
SWRSF: Software Reset Force and Flag
PORSF: Power-On Reset Force and Flag
PINRSF: HW Pin Reset Flag
CNVRSEF
R/W
Bit6
Figure 13.4. RSTSRC: Reset Source Register
C0RSEF
R/W
Bit5
SWRSEF
R/W
Bit4
Rev. 1.7
WDTRSF
Bit3
R
MCDRSF
Bit2
R
PORSF
R/W
Bit1
PINRSF
Bit0
R
SFR Address:
Reset Value
xxxxxxxx
0xEF