C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 250

• Manufacturer Part Number: C8051F020DK
• Description: DEV KIT FOR F020/F021/F022/F023
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F020
• Silicon Family Name: C8051F02x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F020/021/022/023
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1200

C8051F020/1/2/3
23.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the
16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H
into a “snapshot” register; the following PCA0H read accesses this “snapshot” register. Reading the PCA0L Register
first guarantees an accurate reading of the entire 16-bit PCA0 counter. Reading PCA0H or PCA0L does not disturb
the counter operation. The CPS2-CPS0 bits in the PCA0MD register select the timebase for the counter/timer as
shown in Table 23.1. Note that in ‘External oscillator source divided by 8’ mode, the external oscillator source
is synchronized with the system clock, and must have a frequency less than or equal to the system clock.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is set to
logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in PCA0MD to logic 1
enables the CF flag to generate an interrupt request. The CF bit is not automatically cleared by hardware when the
CPU vectors to the interrupt service routine, and must be cleared by software (Note: PCA0 interrupts must be glob-
ally enabled before CF interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit (IE.7)
and the EPCA0 bit in EIE1 to logic 1). Clearing the CIDL bit in the PCA0MD register allows the PCA to continue
normal operation while the CPU is in Idle mode.
250
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
†
‡
External oscillator source divided by 8 is synchronized with the system clock.
The minimum high or low time for the ECI input signal is at least 2 system clock cycles.
CPS2
0
0
0
0
1
1
C
D
L
I
W
D
T
E
PCA0MD
W
D
L
C
K
CPS1
C
P
S
0
0
1
1
0
0
2
000
001
010
011
100
101
C
P
S
1
C
P
S
0
E
C
F
Figure 23.2. PCA Counter/Timer Block Diagram
CPS0
IDLE
Table 23.1. PCA Timebase Input Options
0
1
0
1
0
1
C
F
C
R
PCA0CN
C
C
F
4
Timebase
High-to-low transitions on ECI
C
C
F
3
C
C
F
2
C
C
F
1
C
C
F
0
0
1
Rev. 1.4
PCA0L
External oscillator source divided by 8
read
System clock divided by 12
System clock divided by 4
Snapshot
Register
PCA0H
Timer 0 overflow
System clock
‡
(max rate = system clock divided by 4)
PCA0L
To SFR Bus
To PCA Modules
Overflow
CF
†
To PCA Interrupt System