C8051F410DK Silicon Laboratories Inc, C8051F410DK Datasheet - Page 128

KIT DEV FOR C8051F41X

C8051F410DK

Manufacturer Part Number
C8051F410DK
Description
KIT DEV FOR C8051F41X
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F410DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F41x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F410
Silicon Family Name
C8051F41x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051F41x
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1314

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F410DK
Manufacturer:
Silicon Labs
Quantity:
135
C8051F410/1/2/3
15.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
settles above
DD
V
. An additional delay occurs before the device is released from reset; the delay decreases as the V
RST
DD
ramp time increases (V
ramp time is defined as how fast V
ramps from 0 V to V
). Figure 15.2 plots
DD
DD
RST
the power-on and V
monitor reset timing. For valid ramp times (less than 1 ms), the power-on reset
DD
delay (T
) is typically less than 0.3 ms.
PORDelay
Note: The maximum V
ramp time is 1 ms; slower ramp times may cause the device to be released from
DD
reset before V
reaches the V
level.
DD
RST
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset. The V
monitor is enabled following
DD
a power-on reset.
VDD
V
RS T
1.0
t
/ RST
Logic H IG H
T
P O R D elay
Logic LO W
V D D
P ow er-O n
M onitor
R eset
R eset
Figure 15.2. Power-On and V
Monitor Reset Timing
DD
128
Rev. 1.1

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