C8051F410DK Silicon Laboratories Inc, C8051F410DK Datasheet - Page 147

KIT DEV FOR C8051F41X

C8051F410DK

Manufacturer Part Number
C8051F410DK
Description
KIT DEV FOR C8051F41X
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F410DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F41x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F410
Silicon Family Name
C8051F41x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051F41x
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1314

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F410DK
Manufacturer:
Silicon Labs
Quantity:
135
18. Port Input/Output
Digital and analog resources are available through up to 24 I/O pins. Port pins are organized as three byte-
wide Ports. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input/output;
Port pins P0.0 - P2.7 can be assigned to one of the internal digital resources as shown in Figure 18.3. The
designer has complete control over which functions are assigned, limited only by the number of physical
I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder.
Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regardless of the
Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the peripheral priority
order of the Priority Decoder (Figure 18.3 and Figure 18.4). The registers XBR0 and XBR1, defined in SFR
Definition 18.1 and SFR Definition 18.2, are used to select internal digital functions.
Port I/Os on P0 are 5 V tolerant over the operating range of V
driven above V
configured as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n =
0,1,2). Complete Electrical Specifications for Port I/O are given in Table 18.1 on page 163.
Highest
Priority
Lowest
Priority
SYSCLK
Outputs
IO
SMBus
T0, T1
UART
P0
P1
P2
CP0
CP1
PCA
SPI
or they will sink current. Figure 18.2 shows the Port cell circuit. The Port I/O cells are
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
Figure 18.1. Port I/O Functional Block Diagram
2
4
2
4
7
2
8
8
8
Rev. 1.1
PnSKIP Registers
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
IO
. Port I/Os on P1 and P2 should not be
8
8
8
P0MASK, P0MATCH
P1MASK, P1MATCH
C8051F410/1/2/3
Registers
Cells
Cells
Cell
P0
I/O
P1
I/O
P2
I/O
P2.3–2.6 available on
PnMDIN Registers
C8051F410/2
PnMDOUT,
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
147

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