C8051F410DK Silicon Laboratories Inc, C8051F410DK Datasheet - Page 173

• Manufacturer Part Number: C8051F410DK
• Description: KIT DEV FOR C8051F41X
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F410DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F410
• Silicon Family Name: C8051F41x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F41x
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1314

Note:
Bit7:
Bit6:
Bit5:
Bits4–2: MULDIV: Clock Multiplier Output Scaling Factor
Bits1–0: MULSEL: Clock Multiplier Input Select
MULEN
R/W
Bit7
The maximum SYSCLK is 50 MHz, so the Clock Multiplier output should be scaled accord-
ingly.
MULEN: Clock Multiplier Enable
0: Clock Multiplier disabled.
1: Clock Multiplier enabled.
MULINIT: Clock Multiplier Initialize
This bit should be a ‘0’ when the Clock Multiplier is enabled. Once enabled, writing a ‘1’ to
this bit will initialize the Clock Multiplier. The MULRDY bit reads ‘1’ when the Clock Multiplier
is stabilized.
MULRDY: Clock Multiplier Ready
This read-only bit indicates the status of the Clock Multiplier.
0: Clock Multiplier not ready.
1: Clock Multiplier ready (locked).
These bits scale the Clock Multiplier output.
000: Clock Multiplier Output scaled by a factor of 1.
001: Clock Multiplier Output scaled by a factor of 1.
010: Clock Multiplier Output scaled by a factor of 1.
011: Clock Multiplier Output scaled by a factor of 2/3*.
100: Clock Multiplier Output scaled by a factor of 2/4 (or 1/2).
101: Clock Multiplier Output scaled by a factor of 2/5*.
110: Clock Multiplier Output scaled by a factor of 2/6 (or 1/3).
111: Clock Multiplier Output scaled by a factor of 2/7*.
These bits select the clock supplied to the Clock Multiplier.
*Note: The Clock Multiplier Output duty cycle is not 50% for these settings.
MULINIT MULRDY
R/W
Bit6
SFR Definition 19.4. CLKMUL: Clock Multiplier Control
MULSEL
00
01
10
11
Bit5
R
R/W
Bit4
Selected Input Clock
External Oscillator / 2
Internal Oscillator / 2
External Oscillator
Internal Oscillator
MULDIV
Rev. 1.1
R/W
Bit3
R/W
Bit2
C8051F410/1/2/3
Clock Multiplier Output
External Oscillator x 4
External Oscillator x 2
R/W
Internal Oscillator x 2
Internal Oscillator x 4
Bit1
for MULDIV = 000b
MULSEL
SFR Address:
R/W
Bit0
0xAB
00000000
Reset Value
173