C8051F410DK Silicon Laboratories Inc, C8051F410DK Datasheet - Page 60

• Manufacturer Part Number: C8051F410DK
• Description: KIT DEV FOR C8051F41X
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F410DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F410
• Silicon Family Name: C8051F41x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F41x
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1314

C8051F410/1/2/3
60
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
Bits2–1: AD0RPT1–0: ADC0 Repeat Count.
Bit0:
R/W
Bit7
SAR Conversion clock is derived from FCLK by the following equation, where AD0SC refers
to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements are given in
Table 5.3.
BURSTEN = 0: FCLK is the current system clock.
BURSTEN = 1: FCLK is a maximum of 25 MHz, independent of the current system clock.
*Note: Round the result up.
Controls the number of conversions taken and accumulated between ADC0 End of
Conversion (ADCINT) and ADC0 Window Comparator (ADCWINT) interrupts. A convert
start is required for each conversion unless Burst Mode is enabled. In Burst Mode, a single
convert start can initiate multiple self-timed conversions. Results in both modes are
accumulated in the ADC0H:ADC0L register. When AD0RPT1-0 are set to a value other
than '00', the AD0LJST bit in the ADC0CN register must be set to '0' (right justified).
00: 1 conversion is performed.
01: 4 conversions are performed and accumulated.
10: 8 conversions are performed and accumulated.
11: 16 conversions are performed and accumulated.
Note:
RESERVED. Read = 0b; Must write 0b.
AD0SC
R/W
Bit6
The ADC0 output register is automatically reset to 0x0000 upon reaching the last conversion
specified by the repeat counter. If the ADC is disabled during a conversion and re-enabled later,
the ADC0H and ADC0L registers should be manually cleared to 0x00.
SFR Definition 5.2. ADC0CF: ADC0 Configuration
=
------------------- - 1
CLK
AD0SC
FCLK
R/W
Bit5
SAR
–
*
R/W
Bit4
or
Rev. 1.1
R/W
Bit3
CLK
SAR
R/W
Bit2
=
AD0RPT
----------------------------
AD0SC
FCLK
R/W
Bit1
+
1
Reserved 11111000
R/W
Bit0
SFR Address:
Reset Value
0xBC