C8051F410DK Silicon Laboratories Inc, C8051F410DK Datasheet - Page 69

• Manufacturer Part Number: C8051F410DK
• Description: KIT DEV FOR C8051F41X
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F410DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F410
• Silicon Family Name: C8051F41x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F41x
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1314

6.
The C8051F41x devices include two 12-bit current-mode Digital-to-Analog Converters (IDACs). The maxi-
mum current output of the IDACs can be adjusted for four different current settings; 0.25 mA, 0.5 mA,
1 mA, and 2 mA. The IDACs can be individually enabled or disabled using the enable bits in the corre-
sponding IDAC Control Register (IDA0CN or IDA1CN). When both IDACs are enabled, their outputs may
be routed to individual pins or merged onto a single pin. An internal bandgap bias generator is used to gen-
erate a reference current for the IDACs whenever they are enabled. IDAC updates can be performed on-
demand, scheduled on a Timer overflow, or synchronized with an external pin edge. Figure 6.1 shows a
block diagram of the IDAC circuitry.
6.1.
A flexible output update mechanism allows for seamless full-scale changes and supports jitter-free
updates for waveform generation. Three update modes are provided, allowing IDAC output updates on a
write to the IDAC’s data register, on a Timer overflow, or on an external pin edge.
6.1.1. Update Output On-Demand
In its default mode (IDAnCN.[6:4] = ‘111’) the IDAC output is updated “on-demand” with a write to the data
register high byte (IDAnH). It is important to note that in this mode, writes to the data register low byte
(IDAnL) are held and have no effect on the IDAn output until a write to IDAnH takes place. Since data from
both the high and low bytes of the data register are immediately latched to IDAn after a write to IDAnH, the
write sequence when writing a full 12-bit word to the IDAC data registers should be IDAnL followed
by IDAnH . When the data word is left justified, the IDAC can be used in 8-bit mode by initializing IDAnL to
the desired value (typically 0x00), and writing data only to IDA0H.
12-Bit Current Mode DACs (IDA0 and IDA1)
IDAC Output Scheduling
IDAnOMD1
IDAnOMD0
IDAnRJST
IDAnCM2
IDAnCM1
IDAnCM0
IDAnEN
Figure 6.1. IDAC Functional Block Diagram
8
4
Rev. 1.1
12
IDAn
C8051F410/1/2/3
IDAn
Output
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