C8051F410DK Silicon Laboratories Inc, C8051F410DK Datasheet - Page 78

KIT DEV FOR C8051F41X

C8051F410DK

Manufacturer Part Number
C8051F410DK
Description
KIT DEV FOR C8051F41X
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F410DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F41x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F410
Silicon Family Name
C8051F41x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051F41x
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1314

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F410DK
Manufacturer:
Silicon Labs
Quantity:
135
C8051F410/1/2/3
Important Note About the V
the internal V
should be configured as an analog pin, and skipped by the Digital Crossbar. To configure P1.2 as an ana-
log pin, clear Bit 2 in register P1MDIN to ‘0’ and set Bit 2 in register P1 to '1'. To configure the Crossbar to
skip P1.2, set Bit 2 in register P1SKIP to ‘1’. Refer to
complete Port I/O configuration details. The TEMPE bit in register REF0CN enables/disables the tempera-
ture sensor. While disabled, the temperature sensor defaults to a high impedance state and any ADC0
measurements performed on the sensor result in meaningless data.
78
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
IDAMRG
R/W
Bit7
IDAMRG: IDAC Output Merge Select.
0: IDA1 Output is P0.1.
1: IDA1 Output is P0.0 (Merged with IDA0 Output).
GF. General Purpose Flag.
This bit is a general purpose flag for use under software control.
ZTCEN: Zero-TempCo Bias Enable Bit.
0: ZeroTC Bias Generator automatically enabled when needed.
1: ZeroTC Bias Generator forced on.
REFLV: Voltage Reference Output Level Select.
This bit selects the output voltage level for the internal voltage reference.
0: Internal voltage reference set to 1.5 V.
1: Internal voltage reference set to 2.2 V.
REFSL: Voltage Reference Select.
This bit selects the source for the internal voltage reference.
0: V
1: V
TEMPE: Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
BIASE: Internal Analog Bias Generator Enable Bit.
0: Internal Analog Bias Generator automatically enabled when needed.
1: Internal Analog Bias Generator on.
REFBE: Internal Reference Buffer Enable Bit.
0: Internal Reference Buffer disabled.
1: Internal Reference Buffer enabled. Internal voltage reference driven on the V
REF
REF
DD
. When using either an external voltage reference or the internal reference circuitry, P1.2
R/W
GF
Bit6
used as voltage reference.
pin used as voltage reference.
SFR Definition 7.1. REF0CN: Reference Control
ZTCEN
R/W
Bit5
REF
Pin: Port pin P1.2 is used as the external V
REFLV
R/W
Bit4
Rev. 1.1
REFSL
R/W
Bit3
Section “18. Port Input/Output” on page 147
TEMPE
R/W
Bit2
BIASE
R/W
Bit1
REF
input and as an output for
REFBE
R/W
Bit0
REF
SFR Address:
00000000
Reset Value
pin.
0xD1
for

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