C8051F410DK Silicon Laboratories Inc, C8051F410DK Datasheet - Page 83

• Manufacturer Part Number: C8051F410DK
• Description: KIT DEV FOR C8051F41X
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F410DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F410
• Silicon Family Name: C8051F41x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F41x
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1314

9.
C8051F41x devices include two on-chip programmable voltage comparators: Comparator0 is shown in
Figure 9.1; Comparator1 is shown in Figure 9.2. The two comparators operate identically, but only
Comparator0 can be used as a reset source.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the
system clock is not active. This allows the Comparator to operate and generate an output with the device
in STOP or SUSPEND mode. When assigned to a Port pin, the Comparator output may be configured as
open drain or push-pull (see
be used as a reset source (see
The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 9.2). The CMX0P3-CMX0P0
bits select the Comparator0 positive input; the CMX0N3-CMX0N0 bits select the Comparator0 negative
input. The Comparator1 inputs are selected in the CPT1MX register (SFR Definition 9.4). The CMX1P3-
CMX1P0 bits select the Comparator1 positive input; the CMX1N3-CMX1N0 bits select the Comparator1
negative input.
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be con-
figured as analog inputs in their associated Port configuration register (with a ‘1’ written to the correspond-
ing Port Latch register), and configured to be skipped by the Crossbar (for details on Port configuration,
see
Section “18.3. General Purpose Port I/O” on page 154
P0.1
P0.3
P0.5
P0.7
P1.1
P1.3
P1.5
P1.7
P2.1
P2.3
P2.5
P2.7
Comparators
CMX0N3
CMX0N2
CMX0N1
CMX0N0
CMX0P3
CMX0P2
CMX0P1
CMX0P0
Figure 9.1. Comparator0 Functional Block Diagram
P0.0
P0.2
P0.4
P0.6
P1.0
P1.2
P1.4
P1.6
P2.0
P2.2
P2.4
P2.6
Section “18.2. Port I/O Initialization” on page 151
Section “15.5. Comparator0 Reset” on page 130
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP0OUT
CP0RIF
CP0FIF
CP0EN
CP0 +
CP0 -
Rev. 1.1
+
-
VDD
GND
)
Decision
Reset
Tree
CPT0MD
(SYNCHRONIZER)
D
SET
CLR
Q
Q
C8051F410/1/2/3
D
SET
CLR
Q
Q
Rising-edge
CP0
). Comparator0 may also
).
Crossbar
Interrupt
Logic
Falling-edge
Interrupt
CP0
CP0A
CP0
CP0
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