R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 127

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

5.7
There are two instructions that cause exception handling: trap instruction and illegal instruction.
5.7.1
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state. The trap
instruction exception handling is as follows:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the vector number specified in
A start address is read from the vector table corresponding to a vector number from 0 to 3, as
specified in the instruction code.
Table 5.8 shows the state of CCR and EXR after execution of trap instruction exception handling.
Table 5.8
[Legend]
1: Set to 1
0: Cleared to 0
: Retains the previous value.
Interrupt Control Mode
0
2
the TRAPA instruction is generated, the start address of the exception service routine is loaded
from the vector table to PC, and program execution starts from that address.
Instruction Exception Handling
Trap Instruction
States of CCR and EXR after Trap Instruction Exception Handling
I
1
1
CCR
UI


Rev. 2.00 Sep. 16, 2009 Page 97 of 1036
I2 to I0


Section 5 Exception Handling
EXR
REJ09B0414-0200
T

0