R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 18

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
10.5
10.6
10.7
10.8
10.9
Section 11 I/O Ports........................................................................................... 377
11.1
11.2
Rev. 2.00 Sep. 16, 2009 Page xvi of xxviii
Operation .......................................................................................................................... 355
10.5.1
10.5.2
10.5.3
10.5.4
10.5.5
10.5.6
10.5.7
10.5.8
10.5.9
10.5.10 DTC Bus Release Timing ................................................................................. 368
10.5.11 DTC Priority Level Control to the CPU ........................................................... 368
DTC Activation by Interrupt............................................................................................. 369
Examples of Use of the DTC............................................................................................ 370
10.7.1
10.7.2
10.7.3
Interrupt Sources............................................................................................................... 373
Usage Notes ...................................................................................................................... 373
10.9.1
10.9.2
10.9.3
10.9.4
10.9.5
10.9.6
10.9.7
10.9.8
10.9.9
Register Descriptions........................................................................................................ 384
11.1.1
11.1.2
11.1.3
11.1.4
11.1.5
11.1.6
Output Buffer Control....................................................................................................... 391
11.2.1
Transfer Information Start Address, Source Address, and
Destination Address .......................................................................................... 374
Bus Cycle Division ........................................................................................... 357
Transfer Information Read Skip Function ........................................................ 359
Transfer Information Writeback Skip Function................................................ 360
Normal Transfer Mode ..................................................................................... 360
Repeat Transfer Mode ...................................................................................... 361
Block Transfer Mode ........................................................................................ 363
Chain Transfer .................................................................................................. 364
Operation Timing.............................................................................................. 365
Number of DTC Execution Cycles ................................................................... 367
Normal Transfer Mode ..................................................................................... 370
Chain Transfer .................................................................................................. 370
Chain Transfer when Counter = 0..................................................................... 371
Module Stop Function Setting .......................................................................... 373
On-Chip RAM .................................................................................................. 373
DMAC Transfer End Interrupt.......................................................................... 373
DTCE Bit Setting.............................................................................................. 373
Chain Transfer .................................................................................................. 374
Transfer Information Modification ................................................................... 374
Endian Format .................................................................................................. 374
Points for Caution when Overwriting DTCER ................................................. 375
Data Direction Register (PnDDR) (n = 1 to 3, 6, A, D to F, H, and I).............. 385
Data Register (PnDR) (n = 1 to 3, 6, A, D to F, H, and I) ................................ 386
Port Register (PORTn) (n = 1 to 6, A, D to F, H, and I)................................... 386
Input Buffer Control Register (PnICR) (n = 1 to 6, A, D to F, H, and I).......... 387
Pull-Up MOS Control Register (PnPCR) (n = D to F, H, and I) ...................... 388
Open-Drain Control Register (PnODR) (n = 2 and F)...................................... 390
Port 1................................................................................................................. 391

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