R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 255

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
8.8.4
The number of access cycles in the initial cycle (full access) on the burst ROM interface is
determined by the basic bus interface settings in ABWCR, ASTCR, WTCRA, WTCRB, and bits
CSXHn in CSACR (n = 0 to 7). When area 0 or area 1 designated as burst ROM space is read by
the CPU, the settings in RDNCR and bits CSXTn in CSACR (n = 0 to 7) are ignored.
From one to eight cycles can be selected for the burst cycle, according to the settings of bits
BSTS02 to BSTS00 and BSTS12 to BSTS10 in BROMCR. Wait cycles cannot be inserted. In
addition, 4-word, 8-word, 16-word, or 32-word consecutive burst access can be performed
according to the settings of BSTS01, BSTS00, BSTS11, and BSTS10 bits in BROMCR.
The basic access timing for burst ROM space is shown in figures 8.28 and 8.29.
Upper
Lower
address bus
CSn
AS
RD
Data bus
BS
RD/WR
address bus
Figure 8.28 Example of Burst ROM Access Timing (ASTn = 1, Two Burst Cycles)
Note: n = 1, 0
Basic Timing
T
1
Full access
T
2
T
3
T
1
Rev. 2.00 Sep. 16, 2009 Page 225 of 1036
T
Burst access
2
Section 8 Bus Controller (BSC)
T
1
REJ09B0414-0200
T
2

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