R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 270

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 8 Bus Controller (BSC)
(1)
If consecutive reads in different areas occur while bit IDLS1 in IDLCR is set to 1, idle cycles
specified by bits IDLCA1 and IDLCA0 when bit IDLSELn in IDLCR is cleared to 0, or bits
IDLCB1 and IDLCB0 when bit IDLSELn is set to 1 are inserted at the start of the second read
cycle (n = 0 to 7).
Figure 8.37 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each
being located in a different area. In (a), an idle cycle is not inserted, and a conflict occurs in bus
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data conflict is prevented.
Rev. 2.00 Sep. 16, 2009 Page 240 of 1036
REJ09B0414-0200
Figure 8.37 Example of Idle Cycle Operation (Consecutive Reads in Different Areas)
Bφ
Address bus
CS (area A)
CS (area B)
RD
Data bus
Consecutive Reads in Different Areas
(a) No idle cycle inserted
Bus cycle A
T
1
(IDLS1 = 0)
T
2
T
3
Data hold
time is long.
Bus cycle B
T
1
Data conflict
T
2
(IDLS1 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0)
Bus cycle A
T
1
(b) Idle cycle inserted
T
2
T
3
Bus cycle B
T
i
T
1
T
2