R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 301

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Bit
31
Bit Name
DTE
Initial
Value
0
R/W
R/W
Description
Data Transfer Enable
Enables/disables a data transfer for the corresponding
channel. When this bit is set to 1, it indicates that the
DMAC is in operation.
Setting this bit to 1 starts a transfer when the auto-
request is selected. When the on-chip module interrupt
or external request is selected, a transfer request after
setting this bit to 1 starts the transfer. While data is
being transferred, clearing this bit to 0 stops the
transfer.
In block transfer mode, if writing 0 to this bit while data is
being transferred, this bit is cleared to 0 after the current
1-block size data transfer.
If an event which stops (sustains) a transfer occurs
externally, this bit is automatically cleared to 0 to stop
the transfer.
Operating modes and transfer methods must not be
changed while this bit is set to 1.
0: Disables a data transfer
1: Enables a data transfer (DMA is in operation)
[Clearing conditions]
In block transfer mode, this bit changes after the current
block transfer.
When the specified total transfer size of transfers is
completed
When a transfer is stopped by an overflow interrupt
by a repeat size end
When a transfer is stopped by an overflow interrupt
by an extended repeat size end
When a transfer is stopped by a transfer size error
interrupt
When clearing this bit to 0 to stop a transfer
When an address error or an NMI interrupt is
requested
In the reset state or hardware standby mode
Rev. 2.00 Sep. 16, 2009 Page 271 of 1036
Section 9 DMA Controller (DMAC)
REJ09B0414-0200

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