R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 328

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Section 9 DMA Controller (DMAC)
Figure 9.13 shows an example of timing in cycle stealing mode. The transfer conditions are as
follows:
• Address mode: Single address mode
• Sampling method of the DREQ signal: Low level detection
(2)
In burst mode, once it takes the bus, the DMAC continues a transfer without releasing the bus until
the transfer end condition is satisfied. Even if a transfer is requested from another channel having
priority, the transfer is not stopped once it is started. The DMAC releases the bus in the next cycle
after the transfer for the channel in burst mode is completed. This is similarly to operation in cycle
stealing mode. However, setting the IBCCS bit in IBCR of the bus controller makes the DMAC
release the bus to pass the bus to another bus master.
In block transfer mode, the burst mode setting is ignored (operation is the same as that in burst
mode during one block of transfers). The DMAC is always operated in cycle stealing mode.
Clearing the DTE bit in DMDR stops a DMA transfer. A transfer requested before the DTE bit is
cleared to 0 by the DMAC is executed. When an interrupt by a transfer size error, a repeat size
end, or an extended repeat area overflow occurs, the DTE bit is cleared to 0 and the transfer ends.
Figure 9.14 shows an example of timing in burst mode.
Rev. 2.00 Sep. 16, 2009 Page 298 of 1036
REJ09B0414-0200
Burst Access Mode
Bus cycle
DREQ
Bus cycle
Figure 9.13 Example of Timing in Cycle Stealing Mode
Figure 9.14 Example of Timing in Burst Mode
CPU
CPU
CPU
CPU
DMAC
DMAC
Bus released temporarily for the CPU
No CPU cycle generated
DMAC
CPU
DMAC
DMAC
CPU
CPU
CPU

Related parts for R0K561622S000BE