R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 334

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 DMA Controller (DMAC)
(2)
Figure 9.19 shows the XY conversion using the offset addition in repeat transfer mode.
In figure 9.19, the source address side is specified to the repeat area by DACR and the offset
addition is selected. The offset value is set to 4 × data access size (when the data access size is
longword, H'00000010 is set in DOFR, as an example). The repeat size is set to 4 × data access
size (when the data access size is longword, the repeat size is set to 4 × 4 = 16 bytes, as an
example). The increment or decrement by 1, 2, or 4 is specified as the transfer destination address.
A repeat size end interrupt is requested when the repeat size of transfers is completed.
Rev. 2.00 Sep. 16, 2009 Page 304 of 1036
REJ09B0414-0200
Offset
Offset
Offset
Figure 9.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode
XY Conversion Using Offset
Data 1
Data 2
Data 4
Data 3
1st transfer
Data 1
Data 5
Data 9
Data 13
Data 2
Data 6
Data 10
Data 14
Data 3
Data 7
Data 11
Data 15
Data 4
Data 8
Data 12
Data 16
Data 5
Data 6
Data 7
Data 8
Interrupt
request
generated
Address
initialized
Data 9
Data 10
Data 11
Data 12
2nd transfer
Data 1
Data 5
Data 9
Data 13
Data 2
Data 6
Data 10
Data 14
Data 3
Data 7
Data 11
Data 15
Data 4
Data 8
Data 12
Data 16
Data 13
Data 14
Data 15
Data 16
Transfer source
addresses
changed
by CPU
Transfer
Interrupt
request
generated
Address
initialized
1st transfer
2nd transfer
3rd transfer
4th transfer
3rd transfer
Data 1
Data 5
Data 9
Data 13
Data 2
Data 6
Data 10
Data 14
Data 3
Data 7
Data 11
Data 15
Data 4
Data 8
Data 12
Data 16
Data 1
Data 5
Data 9
Data 13
Transfer source
addresses
changed
by CPU
Interrupt
request
generated
Transfer
Data 2
Data 6
Data 10
Data 14
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data 10
Data 11
Data 12
Data 13
Data 14
Data 15
Data 16
Data 3
Data 7
Data 11
Data 15
1st transfer
2nd transfer
3rd transfer
4th transfer
Data 16
Data 4
Data 8
Data 12