R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 352

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 DMA Controller (DMAC)
(6)
When the NRD bit in DMDR is set to 1, the timing of receiving the next transfer request is
delayed for one cycle.
Figure 9.33 shows an example of normal transfer mode activated by the DREQ signal low level
with NRD = 1.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared. Receiving the next transfer request resumes after completion of the write cycle
and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is
completed.
Bφ
DREQ
Address bus
Channel
Rev. 2.00 Sep. 16, 2009 Page 322 of 1036
REJ09B0414-0200
[1]
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started.
[4][7] Transfer request enable is resumed one cycle after completion of the write cycle.
Activation Timing by DREQ Low Level with NRD = 1
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
request is held.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
Figure 9.33 Example of Transfer in Normal Transfer Mode Activated
[1]
Request
Bus released
Min. of 3 cycles
[2]
Duration of transfer
[3]
request disabled
DMA read
by DREQ Low Level with NRD = 1
cycle
Transfer
source
DMA read
destination
Transfer
Duration of transfer request
cycle
disabled which is extended
Transfer request enable resumed
by NRD
Bus released
[4]
Request
Min. of 3 cycles
[5]
[6]
Duration of transfer
request disabled
DMA read
Transfer
cycle
source
Transfer request enable resumed
DMA read
destination
cycle
Transfer
Duration of transfer request
disabled which is extended
by NRD
Bus released
[7]