R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 362

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Section 9 DMA Controller (DMAC)
9.7.2
Bus Arbitration among DMAC and Other Bus Masters
When DMA transfer cycles are consecutively performed, bus cycles of other bus masters may be
inserted between the transfer cycles. The DMAC can release the bus temporarily to pass the bus to
other bus masters.
The consecutive DMA transfer cycles may not be divided according to the transfer mode settings
to achieve high-speed access.
The read and write cycles of a DMA transfer are not separated. Refreshing, external bus release,
and on-chip bus master (CPU or DTC) cycles are not inserted between the read and write cycles of
a DMA transfer.
In block transfer mode and an auto request transfer by burst access, bus cycles of the DMA
transfer are consecutively performed. For this duration, since the DMAC has priority over the
CPU and DTC, accesses to the external space is suspended (the IBCCS bit in the bus control
register 2 (BCR2) is cleared to 0).
When the bus is passed to another channel or an auto request transfer by cycle stealing, bus cycles
of the DMAC and on-chip bus master are performed alternatively.
When the arbitration function among the DMAC and on-chip bus masters is enabled by setting the
IBCCS bit in BCR2, the bus is used alternatively except the bus cycles which are not separated.
For details, see section 8, Bus Controller (BSC).
A conflict may occur between external space access of the DMAC and an external bus release
cycle. Even if a burst or block transfer is performed by the DMAC, the transfer is stopped
temporarily and a cycle of external bus release is inserted by the BSC according to the external
bus priority (when the CPU external access and the DTC external access do not have priority over
a DMAC transfer, the transfers are not operated until the DMAC releases the bus).
In dual address mode, the DMAC releases the external bus after the external space write cycle.
Since the read and write cycles are not separated, the bus is not released.
An internal space (on-chip memory and internal I/O registers) access of the DMAC and an
external bus release cycle may be performed at the same time.
Rev. 2.00 Sep. 16, 2009 Page 332 of 1036
REJ09B0414-0200

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