R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 378

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 10 Data Transfer Controller (DTC)
10.2.8
DTCCR specifies transfer information read skip.
Rev. 2.00 Sep. 16, 2009 Page 348 of 1036
REJ09B0414-0200
Bit
7 to 5
4
3
Bit
Bit Name
Initial Value
R/W
Note: * Only 0 can be written to clear the flag.
Bit Name

RRS
RCHNE
DTC Control Register (DTCCR)
R/W

7
0
Initial
Value
All 0
0
0
R/W

6
0
R/W
R/W
R/W
R/W
R/W

5
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
DTC Transfer Information Read Skip Enable
Controls the vector address read and transfer
information read. A DTC vector number is always
compared with the vector number for the previous
activation. If the vector numbers match and this bit is
set to 1, the DTC data transfer is started without
reading a vector address and transfer information. If the
previous DTC activation is a chain transfer, the vector
address read and transfer information read are always
performed.
0: Transfer read skip is not performed.
1: Transfer read skip is performed when the vector
Chain Transfer Enable After DTC Repeat Transfer
Enables/disables the chain transfer while transfer
counter (CRAL) is 0 in repeat transfer mode.
In repeat transfer mode, the CRAH value is written to
CRAL when CRAL is 0. Accordingly, chain transfer may
not occur when CRAL is 0. If this bit is set to 1, the
chain transfer is enabled when CRAH is written to
CRAL.
0: Disables the chain transfer after repeat transfer
1: Enables the chain transfer after repeat transfer
numbers match.
RRS
R/W
4
0
RCHNE
R/W
3
0

R
2
0

R
1
0
R/(W)*
ERR
0
0