R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 387

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 10.3 Chain Transfer Conditions
Notes: 1. CRA in normal mode transfer, CRAL in repeat transfer mode, or CRB in block transfer
10.5.1
When the transfer data size is word and the SAR and DAR values are not a multiple of 2, the bus
cycle is divided and the transfer data is read from or written to in bytes. Similarly, when the
transfer data size is longword and the SAR and DAR values are not a multiple of 4, the bus cycle
is divided and the transfer data is read from or written to in words.
Table 10.4 shows the relationship among, SAR, DAR, transfer data size, bus cycle divisions, and
access data size. Figure 10.5 shows the bus cycle division example.
Table 10.4 Number of Bus Cycle Divisions and Access Size
CHNE CHNS DISEL
0
0
0
1
1
1
1
SAR and DAR Values Byte (B)
Address 4n
Address 2n + 1
Address 4n + 2
2. When the contents of the CRAH is written to the CRAL in repeat transfer mode



0
1
1
1
Bus Cycle Division
mode
1st Transfer
0
0
1

0

1
Transfer
Counter*
Not 0
0*

Not 0
0*
Not 0
1 (B)
1 (B)
1 (B)
2
2
1
CHNE CHNS DISEL



0
0
0

0
0
0












2nd Transfer
1 (W)
2 (B-B)
1 (W)
Word (W)
Specified Data Size



0
0
1
0
0
1

Rev. 2.00 Sep. 16, 2009 Page 357 of 1036
Section 10 Data Transfer Controller (DTC)
Transfer
Counter*



Not 0
0*


Not 0
0*

2
2
1
DTC Transfer
Ends at 1st transfer
Ends at 1st transfer
Interrupt request to CPU
Ends at 2nd transfer
Ends at 2nd transfer
Interrupt request to CPU
Ends at 1st transfer
Ends at 2nd transfer
Ends at 2nd transfer
Interrupt request to CPU
Ends at 1st transfer
Interrupt request to CPU
Longword (LW)
1 (LW)
3 (B-W-B)
2 (W-W)
REJ09B0414-0200