R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 477

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
12.3.1
TCR controls the TCNT operation for each channel. The TPU has a total of six TCR registers, one
for each channel. TCR register settings should be made only while TCNT operation is stopped.
Bit
7
6
5
4
3
2
1
0
Bit
Bit Name
Initial Value
R/W
Bit Name
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Timer Control Register (TCR)
CCLR2
R/W
7
0
Initial
Value
0
0
0
0
0
0
0
0
CCLR1
R/W
6
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CCLR0
R/W
5
0
Description
Counter Clear 2 to 0
These bits select the TCNT counter clearing source. See
tables 12.3 and 12.4 for details.
Clock Edge 1 and 0
These bits select the input clock edge. For details, see
table 12.5. When the input clock is counted using both
edges, the input clock period is halved (e.g. Pφ/4 both
edges = Pφ/2 rising edge). If phase counting mode is
used on channels 1, 2, 4, and 5, this setting is ignored
and the phase counting mode setting has priority. Internal
clock edge selection is valid when the input clock is Pφ/4
or slower. This setting is ignored if the input clock is Pφ/1,
or when overflow/underflow of another channel is
selected.
Timer Prescaler 2 to 0
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables 12.6 to 12.11 for details. To select the external
clock as the clock source, the DDR bit and ICR bit for the
corresponding pin should be set to 0 and 1, respectively.
For details, see section 11, I/O Ports.
CKEG1
R/W
4
0
CKEG0
R/W
3
0
Rev. 2.00 Sep. 16, 2009 Page 447 of 1036
Section 12 16-Bit Timer Pulse Unit (TPU)
TPSC2
R/W
2
0
TPSC1
R/W
1
0
REJ09B0414-0200
TPSC0
R/W
0
0

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