R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 546

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 12 16-Bit Timer Pulse Unit (TPU)
(4)
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or
DMAC is activated, the flag is cleared automatically. Figure 12.42 shows the timing for status flag
clearing by the CPU, and figures 12.43 and 12.44 show the timing for status flag clearing by the
DTC or DMAC.
The status flag and interrupt request signal are cleared in synchronization with Pφ after the DTC or
DMAC transfer has started, as shown in figure 12.43. If conflict occurs for clearing the status flag
and interrupt request signal due to activation of multiple DTC or DMAC transfers, it will take up
to five clock cycles (Pφ) for clearing them, as shown in figure 12.44. The next transfer request is
masked for a longer period of either a period until the current transfer ends or a period for five
clock cycles (Pφ) from the beginning of the transfer. Note that in the DTC transfer, the status flag
may be cleared during outputting the destination address.
Rev. 2.00 Sep. 16, 2009 Page 516 of 1036
REJ09B0414-0200
Status Flag Clearing Timing
Pφ
Address
Write
Status flag
Interrupt request
signal
Figure 12.42 Timing for Status Flag Clearing by CPU
TSR write cycle
TSR address
T
1
T
2